IMPLY gate
Appearance
Input A B |
Output A → B | |
0 | 0 | 1 |
0 | 1 | 1 |
1 | 0 | 0 |
1 | 1 | 1 |
The IMPLY gate is an informal digital
logical conditional
.
Symbols
IMPLY can be denoted in algebraic expressions with the logic symbol right-facing arrow (→). Logically, it is equivalent to material implication, and the logical expression ¬A v B.
There are two symbols for IMPLY gates: the traditional symbol and the IEEE symbol. For more information see Logic gate symbols.
Traditional IMPLY Symbol | IEEE IMPLY Symbol |
Functional completeness
While the Implication gate isn't functionally complete by itself, it is in conjunction with the constant 0 source. This can be shown via the following:
Thus as the implication gate with the addition of the constant 0 source can create both the NOT gate and the OR gate, it can create the NOR gate, which is a universal gate.
See also
Wikimedia Commons has media related to IMPLY_gates.
- NIMPLY gate
- AND gate
- NOT gate
- NAND gate
- NOR gate
- XOR gate
- XNOR gate
- Boolean algebra (logic)
- Logic gates