GDDR3 SDRAM

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GDDR3 SDRAM (Graphics Double Data Rate 3 SDRAM) is a type of

The GDDR3 interface transfers two 32 bit wide data words per clock cycle from the I/O pins. Corresponding to the 4n-prefetch a single write or read access consists of a 128 bit wide, one-clock-cycle data transfer at the internal memory core and four corresponding 32 bit wide, one-half-clock-cycle data transfers at the I/O Pins. Single-ended unidirectional Read and Write Data strobes are transmitted simultaneously with Read and Write data respectively in order to capture data properly at the receivers of both the Graphics SDRAM and the controller. Data strobes are organized per byte of the 32 bit wide interface.

Commercial implementation

Despite being designed by

• GDDR3's strobe signal unlike DDR2 SDRAM is unidirectional & single-ended (RDQS, WDQS). This means there is a separate read and write data strobe allowing for a quicker read to write ratio than DDR2.
• GDDR3 has a hardware reset capability allowing it to flush all data from memory and then start again.
• Lower voltage requirements leads to lower power requirements, and lower heat output.
• Higher clock frequencies, due to lower heat output, this is beneficial for increased
  throughput
  and more precise timings.

See also

• List of interface bit rates

References

External links

• JEDEC Standard 3.11.5.7 - GDDR3 Specific SGRAM Functions