TLS acceleration

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Sun Microsystems SSL accelerator PCI card introduced in 2002

TLS acceleration (formerly known as SSL acceleration) is a method of offloading processor-intensive

public-key encryption for Transport Layer Security (TLS) and its predecessor Secure Sockets Layer (SSL)[1]
to a hardware accelerator.

Typically this means having a separate card that plugs into a

PCI slot in a computer that contains one or more coprocessors
able to handle much of the SSL processing.

TLS accelerators may use off-the-shelf

RISC
chips to do most of the difficult computational work.

Principle of TLS acceleration operation

The most computationally expensive part of a TLS session is the TLS handshake, where the TLS server (usually a webserver) and the TLS client (usually a web browser) agree on a number of parameters that establish the security of the connection. During the TLS handshake the server and the client establish session keys (symmetric keys, used for the duration of a given session), but the encryption and signature of the TLS handshake messages itself is done using asymmetric keys, which requires more computational power than the symmetric cryptography used for the encryption/decryption of the session data.

Typically a hardware TLS accelerator will offload processing of the TLS handshake while leaving it to the server software to process the less intense

symmetric cryptography of the actual TLS data exchange, but some accelerators handle all TLS operations and terminate the TLS connection, thus leaving the server seeing only decrypted connections. Sometimes data centers employ dedicated servers for TLS acceleration in a reverse proxy
configuration.

Central processor support

Modern x86 CPUs support Advanced Encryption Standard (AES) encoding and decoding in hardware, using the AES instruction set proposed by Intel in March 2008.

pseudo-random number generator.[2]

See also

References