Logic synthesis
 | This article needs additional citations for verification. (January 2013) |
In
History
The roots of logic synthesis can be traced to the treatment of logic by
The first step toward automation of
Two-level logic circuits are of limited importance in a
Commercial tools
The leading developers and providers of logic synthesis software packages are Synopsys, Cadence, and Siemens. Their synthesis tools are Synopsys Design Compiler, Cadence First Encounter and Siemens Precision RTL.
Logic elements
Logic design is a step in the standard design cycle in which the
Logic operations usually consist of boolean AND, OR, XOR and NAND operations, and are the most basic forms of operations in an electronic circuit. Arithmetic operations are usually implemented with the use of logic operators.
High-level or behavioral
With a goal of increasing designer productivity, research efforts on the synthesis of circuits specified at the behavioral level have led to the emergence of commercial solutions in 2004,[3] which are used for complex ASIC and FPGA design. These tools automatically synthesize circuits specified using high-level languages, like ANSI C/C++ or SystemC, to a register transfer level (RTL) specification, which can be used as input to a gate-level logic synthesis flow.[3] Using high-level synthesis, also known as ESL synthesis, the allocation of work to clock cycles and across structural components, such as floating-point ALUs, is done by the compiler using an optimisation procedure, whereas with RTL logic synthesis (even from behavioural Verilog or VHDL, where a thread of execution can make multiple reads and writes to a variable within a clock cycle) those allocation decisions have already been made.
Multi-level logic minimization
Typical practical implementations of a logic function utilize a multi-level network of logic elements. Starting from an RTL description of a design, the synthesis tool constructs a corresponding multilevel Boolean network.
Next, this network is optimized using several technology-independent techniques before technology-dependent optimizations are performed. The typical cost function during technology-independent optimizations is total literal count of the factored representation of the logic function (which correlates quite well with circuit area).
Finally, technology-dependent optimization transforms the technology-independent circuit into a network of gates in a given technology. The simple cost estimates are replaced by more concrete, implementation-driven estimates during and after technology mapping. Mapping is constrained by factors such as the available gates (logic functions) in the technology library, the drive sizes for each gate, and the delay, power, and area characteristics of each gate.
See also
- Silicon compiler
- Binary decision diagram
- Functional verification
- Boolean differential calculus
- mainframe CPUs and others ICs
References
- ^ "Synthesis:Verilog to Gates" (PDF).
- ISBN 978-0-7923-8393-2.
- ^ a b EETimes: High-level synthesis rollouts enable ESL[permanent dead link]
- Electronic Design Automation For Integrated Circuits Handbook, by Lavagno, Martin, and Scheffer, ISBN 0-8493-3096-3 A survey of the field of Electronic design automation. The above summary was derived, with permission, from Volume 2, Chapter 2, Logic Synthesis by Sunil Khatri and Narendra Shenoy.
Further reading
- Burgun, Luc; Greiner, Alain; Prado Lopes Eudes (October 1994). "A Consistent Approach in Logic Synthesis for FPGA Architectures". Proceedings of the International Conference on ASIC (ASICON). Pekin: 104–107.
- Jiang, Jie-Hong "Roland"; Devadas, Srinivas (2009). "Chapter 6: Logic synthesis in a nutshell". In Wang, Laung-Terng; Chang, Yao-Wen; Cheng, Kwang-Ting (eds.). Electronic design automation: synthesis, verification, and test. Morgan Kaufmann. ISBN 978-0-12-374364-0.
- Hachtel, Gary D.; Somenzi, Fabio (2006) [1996]. Logic Synthesis and Verification Algorithms. ISBN 0-7923-9746-0.
- ISBN 978-0-7923-7606-4.
- Perkowski, Marek A.; Grygiel, Stanislaw (1995-11-20). "6. Historical Overview of the Research on Decomposition". A Survey of Literature on Function Decomposition (PDF). Version IV. Functional Decomposition Group, Department of Electrical Engineering, Portland University, Portland, Oregon, USA. CiteSeerX 10.1.1.64.1129. Archived(PDF) from the original on 2021-03-28. Retrieved 2021-03-28. (188 pages)
- (PDF) from the original on 2017-08-09. Retrieved 2021-03-28. (4+60 pages)
External links
Media related to Logic design at Wikimedia Commons
