14 nm process

Semiconductor device fabrication
MOSFET scaling (process nodes)
0 20 µm  – 1968 010 µm – 1971 00 6 µm  – 1974 00 3 µm  – 1977   1.5 µm  – 1981 00 1 µm  – 1984 800 nm – 1987 600 nm – 1990 350 nm – 1993 250 nm – 1996 180 nm – 1999 130 nm – 2001 090 nm – 2003 065 nm – 2005 045 nm – 2007 032 nm – 2009 028 nm – 2010 022 nm – 2012 014 nm – 2014 010 nm – 2016 007 nm – 2018 005 nm – 2020 003 nm – 2022
Future 002 nm ~ 2024
Half-nodes Density CMOS Device (multi-gate) Moore's law Transistor count Semiconductor Industry Nanoelectronics
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The "14 nanometer process" refers to a marketing term for the

The resolutions of a "14 nm" device are difficult to achieve in a polymeric resist, even with electron beam lithography. In addition, the chemical effects of ionizing radiation also limit reliable resolution to about 30 nm, which is also achievable using current state-of-the-art immersion lithography. Hardmask materials and multiple patterning are required.

A more significant limitation comes from plasma damage to low-k materials. The extent of damage is typically 20 nm thick,^[6] but can also go up to about 100 nm.^[7] The damage sensitivity is expected to get worse as the low-k materials become more porous. For comparison, the atomic radius of an unconstrained silicon is 0.11 nm. Thus about 90 Si atoms would span the channel length, leading to substantial leakage.

Tela Innovations and Sequoia Design Systems developed a methodology allowing double exposure for the "16 nm"/"14 nm" node circa 2010.^[8] Samsung and Synopsys had also, at that time, begun implementing double patterning in "22 nm" and "16 nm" design flows.^[9] Mentor Graphics reported taping out "16 nm" test chips in 2010.^{[10][needs update]} On January 17, 2011, IBM announced that they were teaming up with ARM to develop "14 nm" chip processing technology.^{[11][needs update]}

On February 18, 2011, Intel announced that it would construct a new $5 billion semiconductor fabrication plant in Arizona, designed to manufacture chips using the "14 nm" manufacturing processes and leading-edge 300 mm wafers.^[12][13] The new fabrication plant was to be named Fab 42, and construction was meant to start in the middle of 2011. Intel billed the new facility as "the most advanced, high-volume manufacturing facility in the world," and said it would come on line in 2013. Intel since decided to postpone opening this facility and instead upgrade its existing facilities to support 14-nm chips.^{[14][needs update]} On May 17, 2011, Intel announced a roadmap for 2014 that included "14 nm" transistors for their Xeon, Core, and Atom product lines.^{[15][needs update]}

Technology demos

In the late 1990s, Hisamoto's Japanese team from

In 2005, Toshiba demonstrated a 15 nm FinFET process, with a 15 nm gate length and 10 nm fin width, using a sidewall spacer process.^[18] It had erstwhile been suggested in 2003 that for the 16 nm node, a logic transistor would have a gate length of about 5 nm.^{[19][needs update]} In December 2007, Toshiba demonstrated a prototype memory unit that used 15-nanometre thin lines.^[20]

In December 2009, National Nano Device Laboratories, owned by the Taiwanese government, produced a "16 nm" SRAM chip.^{[21][needs update]}

In September 2011, Hynix announced the development of "15 nm" NAND cells.^{[22][needs update]}

In December 2012, Samsung Electronics taped out a "14 nm" chip.^{[23][needs update]}

In September 2013, Intel demonstrated an Ultrabook laptop that used a "14 nm" Broadwell CPU, and Intel CEO Brian Krzanich said, "[CPU] will be shipping by the end of this year."^[24] However, as of February 2014, shipment had at time erstwhile been delayed further until Q4 2014.^{[25][needs update]}

In August 2014, Intel announced details of the "14 nm" microarchitecture for its upcoming

In 2018 a shortage of "14 nm" fab capacity was announced by Intel.[27]^{[needs update]}

Shipping devices

In 2013,

On September 5, 2014, Intel launched the first three Broadwell-based processors that belonged to the low-TDP Core M family: Core M-5Y10, Core M-5Y10a, and Core M-5Y70.^{[31][needs update]}

In February 2015, Samsung announced that their flagship smartphones, the Galaxy S6 and S6 Edge, would feature "14 nm" Exynos systems on chip (SoCs).^{[32][needs update]}

On March 9, 2015,

On August 2, 2016, Microsoft released the Xbox One S, which utilized "16 nm" by TSMC. ^{[needs update]}

On March 2, 2017, AMD released its Ryzen CPUs based on the Zen architecture, incorporating "14 nm" FinFET technology from Samsung which had erstwhile been licensed to GlobalFoundries for GlobalFoundries to build.^{[39][needs update]}

The NEC SX-Aurora TSUBASA processor, introduced in October 2017,^[40] used a "16 nm" FinFET process from TSMC and was designed for use with NEC SX supercomputers.^{[41][needs update]}

On July 22, 2018, GlobalFoundries announced their "12 nm" Leading-Performance (12LP) process, based on a licensed 14LP process from Samsung.^{[42][needs update]}

In September 2018, Nvidia released GPUs based on their Turing (microarchitecture), which were made on TSMC's "12 nm" process and had a transistor density of 24.67 million transistors per square millimeter.^{[43][needs update]}

14 nm process nodes

Lower numbers are better, except for transistor density, in which case the opposite is true.^[54] Transistor gate pitch is also referred to as CPP (contacted poly pitch), and interconnect pitch is also referred to as MMP (minimum metal pitch).^{[55][56][57][58][59]}

^[60]

References