Racetrack memory

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Racetrack memory or domain-wall memory (DWM) is an experimental

storage density higher than comparable solid-state memory devices like flash memory.[citation needed
]

Description

Racetrack memory uses a

magnetoresistive
sensors, allow the use of much smaller magnetic domains to provide far higher bit densities.

In production, it was expected[citation needed] that the wires could be scaled down to around 50 nm. There were two arrangements considered for racetrack memory. The simplest was a series of flat wires arranged in a grid with read and write heads arranged nearby. A more widely studied arrangement used U-shaped wires arranged vertically over a grid of read/write heads on an underlying substrate. This would allow the wires to be much longer without increasing its 2D area, although the need to move individual domains further along the wires before they reach the read/write heads results in slower random access times. Both arrangements offered about the same throughput performance. The primary concern in terms of construction was practical; whether or not the three dimensional vertical arrangement would be feasible to mass-produce.

Comparison to other memory devices

Projections in 2008 suggested that racetrack memory would offer performance on the order of 20-32 ns to read or write a random bit. This compared to about 10,000,000 ns for a

SRAM, on the order of 0.2 ns, but at a higher cost. Larger feature size "F" of about 45 nm (as of 2011) with a cell area of about 140 F2.[3][4]

Racetrack memory is one among several emerging technologies that aim to replace conventional memories such as DRAM and Flash, and potentially offer a

resistive RAM (RRAM) or spin-torque transfer MRAM
), each of which individually operating much faster (~10 ns).

In most cases, memory devices store one bit in any given location, so they are typically compared in terms of "cell size", a cell storing one bit. Cell size itself is given in units of F², where "F" is the feature size design rule, representing usually the metal line width. Flash and racetrack both store multiple bits per cell, but the comparison can still be made. For instance, hard drives appeared to be reaching theoretical limits around 650 nm²/bit,[5] defined primarily by the capability to read and write to specific areas of the magnetic surface. DRAM has a cell size of about 6 F², SRAM is much less dense at 120 F². NAND flash memory is currently the densest form of non-volatile memory in widespread use, with a cell size of about 4.5 F², but storing three bits per cell for an effective size of 1.5 F². NOR flash memory is slightly less dense, at an effective 4.75 F², accounting for 2-bit operation on a 9.5 F² cell size.[4] In the vertical orientation (U-shaped) racetrack, nearly 10-20 bits are stored per cell, which itself would have a physical size of at least about 20 F². In addition, bits at different positions on the "track" would take different times (from ~10 to ~1000 ns, or 10 ns/bit) to be accessed by the read/write sensor, because the "track" would move the domains at a fixed rate of ~100 m/s past the read/write sensor.

Development challenges

One limitation of the early experimental devices was that the magnetic domains could be pushed only slowly through the wires, requiring current pulses on the orders of microseconds to move them successfully. This was unexpected, and led to performance equal roughly to that of

hard drives, as much as 1000 times slower than predicted. Recent research has traced this problem to microscopic imperfections in the crystal structure of the wires which led to the domains becoming "stuck" at these imperfections. Using an X-ray microscope to directly image the boundaries between the domains, their research found that domain walls would be moved by pulses as short as a few nanoseconds when these imperfections were absent. This corresponds to a macroscopic performance of about 110 m/s.[6]

The voltage required to drive the domains along the racetrack would be proportional to the length of the wire. The current density must be sufficiently high to push the domain walls (as in electromigration). A difficulty for racetrack technology arises from the need for high current density (>108 A/cm2); a 30 nm x 100 nm cross-section would require >3 mA. The resulting power draw becomes higher than that required for other memories, e.g., spin-transfer torque memory (STT-RAM) or flash memory.

Another challenge associated with Racetrack memory is the stochastic nature in which the domain walls move, i.e., they move and stop at random positions.[7] There have been attempts to overcome this challenge by producing notches at the edges of the nanowire.[8] Researchers have also proposed staggered nanowires to pin the domain walls precisely.[9] Experimental investigations have shown[10] the effectiveness of staggered domain wall memory.[11] Recently researchers have proposed non-geometrical approaches such as local modulation of magnetic properties through composition modification. Techniques such as annealing induced diffusion[12] and ion-implantation[13] are used.

See also

References

  1. ^ Spintronics Devices Research, Magnetic Racetrack Memory Project
  2. S2CID 7872869
    .
  3. ^ "ITRS 2011". Retrieved 8 November 2012.
  4. ^
    S2CID 19285283
    .
  5. ^ 1 Tbit/in2 is approx. 650nm²/bit.
  6. ^ Swarup, Amarendra (11 May 2007). "'Racetrack' memory could gallop past the hard disk". New Scientist.
  7. S2CID 67872687
    .
  8. S2CID 7872869
    .
  9. S2CID 201695574
    .
  10. ^ Prem Piramanayagam (24 February 2019), Staggered Domain Wall Memory, archived from the original on 21 December 2021, retrieved 13 March 2019
  11. S2CID 139224277
    .
  12. PMID 29176632
    .
  13. S2CID 52557582
    .

External links

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