Electrochemical RAM
Computer memory and Computer data storage types |
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Volatile |
Non-volatile |
Electrochemical Random-Access Memory (ECRAM) is a type of
Operation
Write
Stress to the gate, relative to channel electrodes, can be applied in the form of fixed current or bias, driving ions toward - or away from - the electrolyte/channel interface where charge transfer occurs with free carriers. Upon insertion in the channel, the ionic charge is neutralized and the atomic species intercalate or bind to the conductive host matrix, in some cases yielding strain and localized phase transformation. Such reversible processes are equivalent to anodic/cathodic reactions in
Read
The read operation is decoupled from the write operation thanks to the presence of three electrodes, therefore limiting read disturb. A small bias is applied between the channel electrodes, with the resulting read current being proportional to the channel conductivity, hence sensing the programmed state of the device.
Speed
The programming speed of ECRAM cells is not limited by the bulk diffusion of ions. They indeed only need to cross the interface plane between the electrolyte and the channel to induce a change in conductivity. Nanosecond write pulses can indeed trigger programming.[8] Trade-offs between gate capacitance, electronic conductivity, etc., can yield settling transients, limiting the maximum read-write frequency.[9]
Arrays
ECRAM arrays are integrated in a pseudo-crossbar layout, the gate access line being common to all devices in a row or column. If a change in
Synaptic function
Principle
Requirements
Metric | Unit | NVM synaptic cell target[11] |
---|---|---|
G range | nS |
9-72 |
on/off ratio | n.a. | 8 |
# of states | n.a. | 1000 |
up/down asymmetry | % | 5 |
write time | ns | 1 |
Physical implementation of artificial neural networks (ANN) must perform at iso-accuracy when benchmarked against
NVM use as synaptic weights in lieu of storage implies significantly different requirements when it comes to target resistance range, number of levels, and programming speed and symmetry. Because the in-memory computation occurs in parallel through the array, many devices are addressed concurrently and therefore need to have a high average resistance to limit energy dissipation. To perform high-accuracy computation and be resilient to noise, the NVM cell needs a large number of distinct states. The programming time needs only to be fast between levels, not from the highest to the lowest resistance states. During each programming cycle (
Demos with ECRAM Synaptic Arrays
Sandia National Laboratories
As reported in a 2019 publication in Science, by Elliot J. Fuller, Alec A. Talin, et al. from Sandia National Laboratories, in collaboration with Stanford University, and the University of Massachusetts Amherst:[10]
Using co-planar organic multilevel cells, isolated by conductive bridge memory (CBM) devices, the team demonstrates parallel programming and addressing in up to 3×3 arrays. In particular a 2-layer neural network is mapped to the array by transferring the weights necessary to perform an inference task resulting in a XOR operation on the binary input vector.
Individual cells are shown to have the following properties (not all achieved in the same device configuration); speed = 1 MHz read-write cycles, number of states > 50 (tunable), resistance range = 50-100 nS (tunable), endurance > 108 write ops, size = 50×50 μm2.
IBM Research
As reported in a 2019 proceeding of the IEEE International Electron Device Meeting (IEDM), by Seyoung Kim, John Rozen, et al. from IBM Research:[6]
Using metal-oxide ECRAM cells, selector-free, the team demonstrates parallel programming and addressing in 2×2 arrays. In particular, a logistic regression task is performed in-memory with 1,000 2×1 vectors as training set. 2D curve fit is achieved in a dozen epochs.
Individual cells are shown to have the following properties (not all achieved in the same device configuration); speed = 10 ns write pulses, number of states > 1,000 (tunable), resistance range = 0-50 μS (tunable), endurance > 107 write ops, size < 1×1 μm2.
Cell implementations
Various institutions have demonstrated ECRAM cells with vastly different materials, layouts, and performances.
An example set for discrete cells is listed in the table.
Ion | Channel | Device Size | Write Pulse Length | Reference |
---|---|---|---|---|
Li+ |
WO 3 |
100 x 100 nm2 | 5 ns | [8] |
Li+ |
Li 1−xCO 2 |
~1 mm2 | 0.5 s | [4] |
Li+ |
Graphene | 36 μm2 | 10 ms | [13] |
Li+ |
α-MO 3 |
~1 mm2 | 10 ms | [14] |
H+ |
PEDOT:PSS | 0.001 mm2 | 5 ms | [5] |
H+ |
WO 3 |
0.05 mm2 | 5 ms | [15] |
H+ |
WO 3 |
0.025 mm2 | 210 ms | [16] |
H+ |
WO 3 |
0.01 mm2 | 0.1 s | [17] |
H+ | 2D MXene | 100 µm2 | 200 ns | [18] |
Li-ECRAM
Based on lithium ions, Li-ECRAM devices have demonstrated repeatable and controlled switching by applying known materials from battery technology to the memory design.[4][13][14] Consequently, such cells can exhibit an OCP which varies over several volts, depending on the programmed state.
H-ECRAM
Based on hydrogen ions, H-ECRAM devices have proven fast, necessitating small driving forces to induce programming.[5][15][16] High diffusion coefficients in various materials can be accompanied by lack of retention within the memory cell, impacting endurance. Most H-ECRAM designs use liquid and/or organic electrolytes. In a 2022 study, researchers at Massachusetts Institute of Technology demonstrated a CMOS-compatible technology based on phosphosilicate glass electrolyte that achieved ultrafast modulation characteristics with high energy efficiency.[7] The same year researchers at the Royal Institute of Technology KTH showed ECRAMS based on hydrogen intercalation into the 2D material MXene, marking the first demonstration of high speed 2D ECRAMs. [18]
MO-ECRAM
Metal-oxide based ECRAM, are inspired from
VLSI
For advanced semiconductor memory or compute applications, a technology needs to be compatible with very large scale integration (VLSI). This puts constraints on materials used, and the techniques employed to fabricate functional devices. The implications for ECRAM are described here.
Semiconductor foundry
A
Back end of line (BEOL)
Memory arrays require logic periphery to operate and interface with the rest of the compute system. Such periphery is based on
Heterogeneous integration (HI)
One way to introduce novel memory materials can be to use
References
- PMID 24177330.
- S2CID 58674536. Retrieved 2020-07-16.
- ^ "Finite element modeling of electrochemical random access memory - iis-projects". iis-projects.ee.ethz.ch. Zürich, Switzerland: ETH Zurich. Retrieved 2020-07-16.
- ^ a b c 'E. J. Fuller et al., Adv. Mater., 29, 1604310 (2017)
- ^ a b c Y. van de Burgt et al., Nature Electronics, 1, 386 (2018)
- ^ S2CID 211211273.
- ^ S2CID 251159631.
- ^ S2CID 58674536.
- ^ D. Bishop et al., proceedings of the international conference in Solid-State Devices and Materials (SSDM), pp. 23-24 (2018)
- ^ S2CID 133605392.
- ^ PMID 27493624.
- PMID 32174807.
- ^ .
- ^ S2CID 104934211.
- ^ PMID 32561717.
- ^ S2CID 49655665.
- ^ J. Lee et al., proceedings of the IEEE international Silicon Nanoelectronics Workshop (SNW), pp. 31-32 (2018)
- ^ S2CID 244484634.
External links
- Moore, S.K. (11 December 2018). "Searching for the Perfect Artificial Synapse for AI". IEEE Spectrum.
- Ambrogio, S.; Adusumilli, P.; Eleftheriou, E. (11 December 2019). "The path to the "perfect" analog material and system: IBM at IEDM and NeurIPS". IBM Research Blog.
- Chandler, D.L. (19 June 2020). "Engineers design a device that operates like a brain synapse". MIT News.
- Kubota, T. (25 April 2019). "Stanford researchers' artificial synapse is fast, efficient and durable". Stanford News.
- "Sandia Powers Breakthroughs in Neuromorphic Computing". inside HPC. 1 May 2019.