Three-dimensional integrated circuit

Source: Wikipedia, the free encyclopedia.

A three-dimensional integrated circuit (3D IC) is a MOS (metal-oxide semiconductor) integrated circuit (IC) manufactured by stacking as many as 16 or more ICs and interconnecting them vertically using, for instance, through-silicon vias (TSVs) or Cu-Cu connections,[1] so that they behave as a single device to achieve performance improvements at reduced power and smaller footprint than conventional two dimensional processes. The 3D IC is one of several 3D integration schemes that exploit the z-direction to achieve electrical performance benefits in microelectronics and nanoelectronics.

3D integrated circuits can be classified by their level of interconnect hierarchy at the global (package), intermediate (bond pad) and local (transistor) level.[2] In general, 3D integration is a broad term that includes such technologies as 3D wafer-level packaging (3DWLP); 2.5D and 3D interposer-based integration; 3D stacked ICs (3D-SICs); 3D heterogeneous integration; and 3D systems integration;[3][4] as well as true monolithic 3D ICs.

International organizations such as the Jisso Technology Roadmap Committee (JIC) and the

NAND flash memory and in mobile devices
.

Types

3D ICs vs. 3D Packaging

3D packaging refers to 3D integration schemes that rely on traditional interconnection methods such as

package on package (PoP) configurations interconnected with wire bonds or flip chip technology. PoP is used for vertically integrating disparate technologies. 3D WLP uses wafer level processes such as redistribution layers
(RDLs) and wafer bumping processes to form interconnects.

2.5D interposer is a 3D WLP that interconnects dies side-by-side on a silicon, glass, or organic interposer using through silicon vias (TSVs) and an RDL. In all types of 3D packaging, chips in the package communicate using off-chip signaling, much as if they were mounted in separate packages on a normal printed circuit board. The interposer may be made of silicon, and is under the dies it connects together. A design can be split into several dies, and then mounted on the interposer with micro bumps.[6][7][8]

3D ICs can be divided into 3D Stacked ICs (3D SIC), which refers to

V-NAND devices.[12]

As of the 2010s, 3D IC packages are widely used for

mobile devices.[13]

One master die and three slave dies

3D SiCs

The digital electronics market requires a higher density

DDR4 (double-data rate 4) memory using 3D TSV package technology.[14] Newer proposed standards for 3D stacked DRAM include Wide I/O, Wide I/O 2, Hybrid Memory Cube, High Bandwidth Memory
.

Monolithic 3D ICs

True monolithic 3D ICs are built in layers on a single

diced into 3D ICs. There is only one substrate, hence no need for aligning, thinning, bonding, or through-silicon vias
. In general, monolithic 3D ICs are still a developing technology and are considered by most to be several years away from production.

Process temperature limitations can be addressed by partitioning the transistor fabrication into two phases. A high temperature phase which is done before layer transfer followed by a layer transfer using ion-cut, also known as layer transfer, which has been used to produce Silicon on Insulator (SOI) wafers for the past two decades. Multiple thin (10s–100s nanometer scale) layers of virtually defect-free Silicon can be created by utilizing low temperature (<400 °C) bond and cleave techniques, and placed on top of active transistor circuitry, followed by permanent finalization of the transistors using etch and deposition processes. This monolithic 3D IC technology has been researched at Stanford University under a DARPA-sponsored grant.

CEA-Leti also developed monolithic 3D IC approaches, called sequential 3D IC. In 2014, the French research institute introduced its CoolCube™, a low-temperature process flow that provides a true path to 3DVLSI.[15]

At Stanford University, researchers designed monolithic 3D ICs using carbon nanotube (CNT) structures vs. silicon using a wafer-scale low temperature CNT transfer processes that can be done at 120 °C.[16]

Manufacturing Technologies for 3D SiCs

There are several methods for 3D IC design, including recrystallization and wafer bonding methods. There are two major types of wafer bonding, Cu-Cu connections (copper-to-copper connections between stacked ICs, used in TSVs)[17][18] and through-silicon via (TSV). 3D ICs with TSVs may use solder microbumps, small solder balls as an interface between two individual dies in a 3D IC.[19] As of 2014, a number of memory products such as High Bandwidth Memory (HBM) and the Hybrid Memory Cube have been launched that implement 3D IC stacking with TSVs. There are a number of key stacking approaches being implemented and explored. These include die-to-die, die-to-wafer, and wafer-to-wafer.

Die-to-Die
Electronic components are built on multiple die, which are then aligned and bonded. Thinning and TSV creation may be done before or after bonding. One advantage of die-to-die is that each component die can be tested first, so that one bad die does not ruin an entire stack.[20] Moreover, each die in the 3D IC can be binned beforehand, so that they can be mixed and matched to optimize power consumption and performance (e.g. matching multiple dice from the low power process corner for a mobile application).
Die-to-Wafer
Electronic components are built on two semiconductor wafers. One wafer is diced; the singulated dice are aligned and bonded onto die sites of the second wafer. As in the wafer-on-wafer method, thinning and TSV creation are performed either before or after bonding. Additional die may be added to the stacks before dicing.[21]
Wafer-to-Wafer
CMOS logic or DRAM
(typically 300 mm), complicating heterogeneous integration.

Benefits

While traditional CMOS scaling processes improves signal propagation speed, scaling from current manufacturing and chip-design technologies is becoming more difficult and costly, in part because of power-density constraints, and in part because interconnects do not become faster while transistors do.[22] 3D ICs address the scaling challenge by stacking 2D dies and connecting them in the 3rd dimension. This promises to speed up communication between layered chips, compared to planar layout.[23] 3D ICs promise many significant benefits, including:

Footprint
More functionality fits into a small space. This extends Moore's law and enables a new generation of tiny but powerful devices.
Cost
Partitioning a large chip into multiple smaller dies with 3D stacking can improve the yield and reduce the fabrication cost if individual dies are tested separately.[24][25]
Heterogeneous Integration
Circuit layers can be built with different processes, or even on different types of wafers. This means that components can be optimized to a much greater degree than if they were built together on a single wafer. Moreover, components with incompatible manufacturing could be combined in a single 3D IC.[26][4]
Shorter Interconnect
The average wire length is reduced. Common figures reported by researchers are on the order of 10–15%, but this reduction mostly applies to longer interconnect, which may affect circuit delay by a greater amount. Given that 3D wires have much higher capacitance than conventional in-die wires, circuit delay may or may not improve.
Power
Keeping a signal on-chip can reduce its
power consumption by 10–100 times.[27] Shorter wires also reduce power consumption by producing less parasitic capacitance.[28]
Reducing the power budget leads to less heat generation, extended battery life, and lower cost of operation.
Design
The vertical dimension adds a higher order of connectivity and offers new design possibilities.[4]
Circuit Security
3D integration can achieve
electronic system
against run-time attacks as well as malicious hardware modifications.
Bandwidth
3D integration allows large numbers of vertical vias between the layers. This allows construction of wide bandwidth
memory wall problem.[31]

Challenges

Because this technology is new, it carries new challenges, including:

Cost
While cost is a benefit when compared with scaling, it has also been identified as a challenge to the commercialization of 3D ICs in mainstream consumer applications. However, work is being done to address this. Although 3D technology is new and fairly complex, the cost of the manufacturing process is surprisingly straightforward when broken down into the activities that build up the entire process. By analyzing the combination of activities that lay at the base, cost drivers can be identified. Once the cost drivers are identified, it becomes a less complicated endeavor to determine where the majority of cost comes from and, more importantly, where cost has the potential to be reduced.[32]
Yield
Each extra manufacturing step adds a risk for defects. In order for 3D ICs to be commercially viable, defects could be repaired or tolerated, or defect density can be improved.[33][34]
Heat
Heat building up within the stack must be dissipated. This is an inevitable issue as electrical proximity correlates with thermal proximity. Specific thermal hotspots must be more carefully managed.
Design Complexity
Taking full advantage of 3D integration requires sophisticated design techniques and new CAD tools.[35]
TSV-introduced Overhead
TSVs are large compared to gates and impact floorplans. At the 45 nm technology node, the area footprint of a 10μm x 10μm TSV is comparable to that of about 50 gates.[36] Furthermore, manufacturability demands landing pads and keep-out zones which further increase TSV area footprint. Depending on the technology choices, TSVs block some subset of layout resources.[36] Via-first TSVs are manufactured before metallization, thus occupy the device layer and result in placement obstacles. Via-last TSVs are manufactured after metallization and pass through the chip. Thus, they occupy both the device and metal layers, resulting in placement and routing obstacles. While the usage of TSVs is generally expected to reduce wirelength, this depends on the number of TSVs and their characteristics.[36] Also, the granularity of inter-die partitioning impacts wirelength. It typically decreases for moderate (blocks with 20-100 modules) and coarse (block-level partitioning) granularities, but increases for fine (gate-level partitioning) granularities.[36]
Testing
To achieve high overall yield and reduce costs, separate testing of independent dies is essential.[34][37] However, tight integration between adjacent active layers in 3D ICs entails a significant amount of interconnect between different sections of the same circuit module that were partitioned to different dies. Aside from the massive overhead introduced by required TSVs, sections of such a module, e.g., a multiplier, cannot be independently tested by conventional techniques. This particularly applies to timing-critical paths laid out in 3D.
Lack of Standards
There are few standards for TSV-based 3D IC design, manufacturing, and packaging, although this issue is being addressed.[38][39] In addition, there are many integration options being explored such as via-last, via-first, via-middle;[40] interposers[41] or direct bonding; etc.
Heterogeneous Integration Supply Chain
In heterogeneously integrated systems, the delay of one part from one of the different parts suppliers delays the delivery of the whole product, and so delays the revenue for each of the 3D IC part suppliers.
Lack of Clearly Defined Ownership
It is unclear who should own the 3D IC integration and packaging/assembly. It could be assembly houses like
OEMs
.

Design Styles

Depending on partitioning granularity, different design styles can be distinguished. Gate-level integration faces multiple challenges and currently appears less practical than block-level integration.[42]

Gate-level Integration
This style partitions standard cells between multiple dies. It promises wirelength reduction and great flexibility. However, wirelength reduction may be undermined unless modules of certain minimal size are preserved. On the other hand, its adverse effects include the massive number of necessary TSVs for interconnects. This design style requires 3D
tested before die stacking. After die stacking (post-bond testing), a single failed die can render several good dies unusable, undermining yield. This style also amplifies the impact of process variation, especially inter-die variation. In fact, a 3D layout may yield more poorly than the same circuit laid out in 2D, contrary to the original promise of 3D IC integration.[43] Furthermore, this design style requires to redesign available Intellectual Property, since existing IP blocks
and EDA tools do not provision for 3D integration.
Block-level Integration
This style assigns entire design blocks to separate dies. Design blocks subsume most of the
last-minute engineering changes
. Restricting the impact of such changes to single dies is essential to limit cost.

History

Several years after the

memory chip was proposed by NEC researchers Katsuhiro Onoda, Ryo Igarashi, Toshio Wada, Sho Nakanuma and Toru Tsujide.[47]

Arm has made a high-density 3D logic test chip,[48] and Intel with its Foveros 3D logic chip packing is planning to ship CPUs using it.[49] IBM demonstrated a fluid that could be used for both power delivery and cooling 3D ICs.[50]

Demonstrations (1983–2012)

Japan (1983–2005)

3D ICs were first successfully demonstrated in

silicon-on-insulator (SOI) CMOS structure.[53] The following year, they fabricated a 3D gate array with vertically stacked dual SOI/CMOS structure using beam recrystallization.[54]

In 1986,

optical sensor, level detector, memory and ALU.[59]

The most common form of 3D IC design is wafer bonding.

NMOS FET lower layer and a thinned NMOS FET upper layer, and proposed CUBIC technology that could fabricate 3D ICs with more than three active layers.[55][51][60]

The first 3D IC stacked chips fabricated with a

LSI chip in 1989.[51][61][62] In 1999, the Association of Super-Advanced Electronics Technologies (ASET) in Japan began funding the development of 3D IC chips using TSV technology, called the "R&D on High Density Electronic System Integration Technology" project.[51][63] The term "through-silicon via" (TSV) was coined by Tru-Si Technologies researchers Sergey Savastiouk, O. Siniaguine, and E. Korczynski, who proposed a TSV method for a 3D wafer-level packaging (WLP) solution in 2000.[64]

The Koyanagi Group at

system-on-a-chip (SoC) design.[65][66]

In 2001, a Toshiba research team including T. Imoto, M. Matsui and C. Takubo developed a "System Block Module" wafer bonding process for manufacturing 3D IC packages.[55][67]

Europe (1988–2005)

Fraunhofer and Siemens began research on 3D IC integration in 1987.[51] In 1988, they fabricated 3D CMOS IC devices based on re-crystallization of poly-silicon.[68] In 1997, the inter-chip via (ICV) method was developed by a Fraunhofer–Siemens research team including Peter Ramm, Manfred Engelhardt, Werner Pamler, Christof Landesberger and Armin Klumpp.[69] It was a first industrial 3D IC process, based on Siemens CMOS fab wafers. A variation of that TSV process was later called TSV-SLID (solid liquid inter-diffusion) technology.[70] It was an approach to 3D IC design based on low temperature wafer bonding and vertical integration of IC devices using inter-chip vias, which they patented.

Ramm went on to develop industry-academic consortia for production of relevant 3D integration technologies. In the German funded cooperative VIC project between Siemens and Fraunhofer, they demonstrated a complete industrial 3D IC stacking process (1993–1996). With his Siemens and Fraunhofer colleagues, Ramm published results showing the details of key processes such as 3D metallization [T. Grassl, P. Ramm, M. Engelhardt, Z. Gabric, O. Spindler, First International Dielectrics for VLSI/ULSI Interconnection Metallization Conference – DUMIC, Santa Clara, CA, 20–22 Feb, 1995] and at ECTC 1995 they presented early investigations on stacked memory in processors.[71]

In the early 2000s, a team of Fraunhofer and Infineon Munich researchers investigated 3D TSV technologies with particular focus on die-to-substrate stacking within the German/Austrian EUREKA project VSI and initiated the European Integrating Projects e-CUBES, as a first European 3D technology platform, and e-BRAINS with a.o., Infineon, Siemens, EPFL, IMEC and Tyndall, where heterogeneous 3D integrated system demonstrators were fabricated and evaluated. A particular focus of the e-BRAINS project was the development of novel low-temperature processes for highly reliable 3D integrated sensor systems.[72]

United States (1999–2012)

Copper-to-copper wafer bonding, also called Cu-Cu connections or Cu-Cu wafer bonding, was developed at

MIT by a research team consisting of Andy Fan, Adnan-ur Rahman and Rafael Reif in 1999.[18][73] Reif and Fan further investigated Cu-Cu wafer bonding with other MIT researchers including Kuan-Neng Chen, Shamik Das, Chuan Seng Tan and Nisha Checka during 2001–2002.[18] In 2003, DARPA and the Microelectronics Center of North Carolina (MCNC) began funding R&D on 3D IC technology.[51]

In 2004, Tezzaron Semiconductor[74] built working 3D devices from six different designs.[75] The chips were built in two layers with "via-first" tungsten TSVs for vertical interconnection. Two wafers were stacked face-to-face and bonded with a copper process. The top wafer was thinned and the two-wafer stack was then diced into chips. The first chip tested was a simple memory register, but the most notable of the set was an 8051 processor/memory stack[76] that exhibited much higher speed and lower power consumption than an analogous 2D assembly.

In 2004, Intel presented a 3D version of the Pentium 4 CPU.[77] The chip was manufactured with two dies using face-to-face stacking, which allowed a dense via structure. Backside TSVs are used for I/O and power supply. For the 3D floorplan, designers manually arranged functional blocks in each die aiming for power reduction and performance improvement. Splitting large and high-power blocks and careful rearrangement allowed to limit thermal hotspots. The 3D design provides 15% performance improvement (due to eliminated pipeline stages) and 15% power saving (due to eliminated repeaters and reduced wiring) compared to the 2D Pentium 4.

The Teraflops Research Chip introduced in 2007 by Intel is an experimental 80-core design with stacked memory. Due to the high demand for memory bandwidth, a traditional I/O approach would consume 10 to 25 W.[37] To improve upon that, Intel designers implemented a TSV-based memory bus. Each core is connected to one memory tile in the SRAM die with a link that provides 12 GB/s bandwidth, resulting in a total bandwidth of 1 TB/s while consuming only 2.2 W.

An academic implementation of a 3D processor was presented in 2008 at the University of Rochester by Professor Eby Friedman and his students. The chip runs at a 1.4 GHz and it was designed for optimized vertical processing between the stacked chips which gives the 3D processor abilities that the traditional one layered chip could not reach.[78] One challenge in manufacturing of the three-dimensional chip was to make all of the layers work in harmony without any obstacles that would interfere with a piece of information traveling from one layer to another.[79]

In ISSCC 2012, two 3D-IC-based multi-core designs using GlobalFoundries' 130 nm process and Tezzaron's FaStack technology were presented and demonstrated:

  • 3D-MAPS,
    Georgia Institute of Technology
    .
  • Centip3De,[81] near-threshold design based on ARM Cortex-M3 cores, was from the Department of Electrical Engineering and Computer Science at University of Michigan.

Commercial 3D ICs (2004–present)

system-in-package
.

The earliest known commercial use of a 3D IC chip was in

chip-on-chip" (CoC) solution.[13][82]

In April 2007, Toshiba commercialized an eight-layer 3D IC, the 16 

mobile devices.[13]

30 nm class) based on TSV in September, and then Samsung and Micron Technology announced TSV-based Hybrid Memory Cube (HMC) technology in October.[87]

Cut through a graphics card that uses High Bandwidth Memory (HBM), based on through-silicon via (TSV) 3D IC technology.

HBM2, at up to 8 GB per stack.[89][90]

In 2017, Samsung Electronics combined 3D IC stacking with its 3D 

TB flash chip with 16 stacked V-NAND dies.[92][93] As of 2018, Intel is considering the use of 3D ICs to improve performance.[94] As of 2022, 232-layer NAND, i.e. memory device, chips are made by Micron,[95]
that previously in April 2019 were making 96-layer chips; and Toshiba made 96-layer devices in 2018.

In 2022, AMD has introduced Zen 4 processors, and some Zen 4 processors have 3D Cache included.

See also

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References

Further reading

External links
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