Hardware description language
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In computer engineering, a hardware description language (HDL) is a specialized computer language used to describe the structure and behavior of electronic circuits, most commonly to design ASICs and program FPGAs.
A hardware description language enables a precise,
A hardware description language looks much like a programming language such as C or ALGOL; it is a textual description consisting of expressions, statements and control structures. One important difference between most programming languages and HDLs is that HDLs explicitly include the notion of time.
HDLs form an integral part of electronic design automation (EDA) systems, especially for complex circuits, such as application-specific integrated circuits, microprocessors, and programmable logic devices.
Motivation
Due to the exploding complexity of digital electronic circuits since the 1970s (see
There are two major hardware description languages: VHDL and Verilog. There are different types of description in them: "dataflow, behavioral and structural". Example of dataflow of VHDL:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY not1 IS
PORT(
a : IN STD_LOGIC;
b : OUT STD_LOGIC;
);
END not1;
ARCHITECTURE behavioral OF not1 IS
BEGIN
b <= NOT a;
END behavioral;
Structure of HDL
HDLs are standard text-based expressions of the structure of electronic systems and their behaviour over time. Like
HDLs are used to write executable specifications for hardware. A program designed to implement the underlying semantics of the language statements and simulate the progress of time provides the hardware designer with the ability to model a piece of hardware before it is created physically. It is this executability that gives HDLs the illusion of being
Comparison with control-flow languages
It is certainly possible to represent hardware semantics using traditional programming languages such as
Using the proper subset of hardware description language, a program called a synthesizer, or logic synthesis tool, can infer hardware logic operations from the language statements and produce an equivalent netlist of generic hardware primitives[jargon] to implement the specified behaviour.[citation needed] Synthesizers generally ignore the expression of any timing constructs in the text. Digital logic synthesizers, for example, generally use clock edges as the way to time the circuit, ignoring any timing constructs. The ability to have a synthesizable subset of the language does not itself make a hardware description language.
History
The first hardware description languages appeared in the late 1960s, looking like more traditional languages.
The language became more widespread with the introduction of DEC's PDP-16 RT-Level Modules (RTMs) and a book describing their use.[5] At least two implementations of the basic ISP language (ISPL and ISPS) followed.[6][7] ISPS was well suited to describe relations between the inputs and the outputs of the design and was quickly adopted by commercial teams at DEC, as well as by a number of research teams both in the US and among its NATO allies.
The RTM products never took off commercially and DEC stopped marketing them in the mid-1980s, as new techniques and in particular
Separate work done about 1979 at the
By the late 1970s, design using programmable logic devices (PLDs) became popular, although these designs were primarily limited to designing finite-state machines. The work at Data General in 1980 used these same devices to design the Data General Eclipse MV/8000, and commercial need began to grow for a language that could map well to them. By 1983 Data I/O introduced ABEL to fill that need.
In 1985, as design shifted to VLSI,
The introduction of
Within a few years, VHDL and Verilog emerged as the dominant HDLs in the electronics industry, while older and less capable HDLs gradually disappeared from use. However, VHDL and Verilog share many of the same limitations, such as being unsuitable for analog or mixed-signal circuit simulation. Specialized HDLs (such as Confluence) were introduced with the explicit goal of fixing specific limitations of Verilog and VHDL, though none were ever intended to replace them.
Over the years, much effort has been invested in improving HDLs. The latest iteration of Verilog, formally known as IEEE 1800-2005 SystemVerilog, introduces many new features (classes, random variables, and properties/assertions) to address the growing need for better test bench randomization, design hierarchy, and reuse. A future revision of VHDL is also in development[when?], and is expected to match SystemVerilog's improvements.
Design using HDL
As a result of the efficiency gains realized using HDL, a majority of modern digital circuit design revolves around it. Most designs begin as a set of requirements or a high-level architectural diagram. Control and decision structures are often prototyped in flowchart applications, or entered in a editor. The process of writing the HDL description is highly dependent on the nature of the circuit and the designer's preference for coding style. The HDL is merely the 'capture language', often beginning with a high-level algorithmic description such as a C++ mathematical model. Designers often use scripting languages such as Perl to automatically generate repetitive circuit structures in the HDL language. Special text editors offer features for automatic indentation, syntax-dependent coloration, and macro-based expansion of the entity/architecture/signal declaration.
The HDL code then undergoes a code review, or auditing. In preparation for synthesis, the HDL description is subject to an array of automated checkers. The checkers report deviations from standardized code guidelines, identify potential ambiguous code constructs before they can cause misinterpretation, and check for common logical coding errors, such as floating ports or shorted outputs. This process aids in resolving errors before the code is synthesized.
In industry parlance, HDL design generally ends at the synthesis stage. Once the synthesis tool has mapped the HDL description into a gate netlist, the netlist is passed off to the back-end stage. Depending on the physical technology (FPGA, ASIC gate array, ASIC standard cell), HDLs may or may not play a significant role in the back-end flow. In general, as the design flow progresses toward a physically realizable form, the design database becomes progressively more laden with technology-specific information, which cannot be stored in a generic HDL description. Finally, an integrated circuit is manufactured or programmed for use.
Simulating and debugging HDL code
Essential to HDL design is the ability to simulate HDL programs. Simulation allows an HDL description of a design (called a model) to pass design verification, an important milestone that validates the design's intended function (specification) against the code implementation in the HDL description. It also permits architectural exploration. The engineer can experiment with design choices by writing multiple variations of a base design, then comparing their behavior in simulation. Thus, simulation is critical for successful HDL design.
To simulate an HDL model, an engineer writes a top-level simulation environment (called a
Design verification is often the most time-consuming portion of the design process, due to the disconnect between a device's functional specification, the designer's interpretation of the specification, and the imprecision[citation needed] of the HDL language. The majority of the initial test/debug cycle is conducted in the HDL simulator environment, as the early stage of the design is subject to frequent and major circuit changes. An HDL description can also be prototyped and tested in hardware — programmable logic devices are often used for this purpose. Hardware prototyping is comparatively more expensive than HDL simulation, but offers a real-world view of the design. Prototyping is the best way to check interfacing against other hardware devices and hardware prototypes. Even those running on slow FPGAs offer much shorter simulation times than pure HDL simulation.
Design verification with HDLs
Historically, design verification was a laborious, repetitive loop of writing and running simulation test cases against the design under test. As chip designs have grown larger and more complex, the task of design verification has grown to the point where it now dominates the schedule of a design team. Looking for ways to improve design productivity, the electronic design automation industry developed the Property Specification Language.
In
The assertions do not model circuit activity, but capture and document the designer's intent in the HDL code. In a simulation environment, the simulator evaluates all specified assertions, reporting the location and severity of any violations. In a synthesis environment, the synthesis tool usually operates with the policy of halting synthesis upon any violation. Assertion based verification is still in its infancy, but is expected to become an integral part of the HDL design toolset.
HDL and programming languages
An HDL is grossly similar to a software
Both programming languages and HDLs are processed by a compiler (often called a synthesizer in the HDL case), but with different goals. For HDLs, "compiling" refers to
On the other hand, a software compiler converts the source-code listing into a microprocessor-specific object code for execution on the target microprocessor. As HDLs and programming languages borrow concepts and features from each other, the boundary between them is becoming less distinct. However, pure HDLs are unsuitable for general purpose application software development,[why?] just as general-purpose programming languages are undesirable for modeling hardware.
Yet as electronic systems grow increasingly complex, and
The high level of abstraction of SystemC models is well suited to early architecture exploration, as architectural modifications can be easily evaluated with little concern for signal-level implementation issues. However, the threading model used in SystemC relies on shared memory, causing the language not to handle parallel execution or low-level models well.
High-level synthesis
In their level of abstraction, HDLs have been compared to assembly languages.[citation needed] There are attempts to raise the abstraction level of hardware design in order to reduce the complexity of programming in HDLs, creating a sub-field called high-level synthesis.
Companies such as
A similar initiative from Intel is the use of Data Parallel C++, related to SYCL, as a high-level synthesis language.
Annapolis Micro Systems, Inc.'s CoreFire Design Suite
It is also possible to design hardware modules using MATLAB and Simulink using the MathWorks HDL Coder tool[12] or DSP Builder for Intel FPGAs[13] or Xilinx System Generator (XSG) from Xilinx.[14]
Examples of HDLs
HDLs for analog circuit design
Name | Description |
---|---|
HDL-A | A proprietary analog HDL |
SpectreHDL | A proprietary analog HDL from Cadence Design Systems for its Spectre circuit simulator |
Verilog-AMS (Verilog for Analog and Mixed-Signal) | An Accellera standard extension of IEEE Std 1364 Verilog for analog and mixed-signal simulation |
VHDL-AMS (VHDL with Analog/Mixed-Signal extension) | An IEEE standard extension (IEEE Std 1076.1) of VHDL for analog and mixed-signal simulation |
HDLs for digital circuit design
The two most widely used and well-supported HDL varieties used in industry are Verilog and VHDL.
Status | Name | Host Language | Description |
---|---|---|---|
In Use | Altera Hardware Description Language (AHDL) | A proprietary language from Altera | |
AHPL (A Hardware Programming language) | Used as a tool for teaching | ||
Amaranth | Python | ||
Bluespec | High-level HDL based on | ||
Bluespec SystemVerilog (BSV)
|
Based on Bluespec, Inc.
| ||
C-to-Verilog | Converter from C to Verilog | ||
Chisel (Constructing Hardware in a Scala Embedded Language)[16] | Scala | Based on Scala (embedded DSL) | |
Clash | Clash is a functional hardware description language that borrows both its syntax and semantics from the functional programming language Haskell | ||
COLAMO (Common Oriented Language for Architecture of Multi Objects)[17] | A proprietary language from “Supercomputers and Neurocomputers Research Center” Co Ltd. | ||
CUPL (Compiler for Universal Programmable Logic)[18] | A proprietary language from Logical Devices, Inc. | ||
DSLX | A domain-specific language targeting the XLS toolchain | ||
ESys.net | .NET framework written in C# | ||
Handel-C | A C-like design language | ||
Hardcaml | OCaml | Based on OCaml (embedded DSL). Try it online. | |
HHDL | Haskell | Based on Haskell (embedded DSL).
| |
Hardware Join Java (HJJ) | Join Java | Based on Join Java | |
HML (Hardware ML) | Standard ML | Based on Standard ML[19] | |
Hydra | Haskell | Based on Haskell
| |
Impulse C | C-like HDL | ||
ParC (Parallel C++) | kusu extended with HDL style threading and communication for task-parallel programming | ||
JHDL | Java | Based on Java | |
Lava | Haskell | Based on | |
Lola
|
A simple language used for teaching | ||
M | A HDL from Mentor Graphics | ||
MyHDL | Python | Based on Python (embedded DSL) | |
PALASM | For Programmable Array Logic (PAL) devices | ||
PipelineC | C-like hardware description language adding High-level synthesis-like automatic pipelining as a language construct/compiler feature. | ||
PyMTL 3 (Mamba) | Python | Based on Python, from Cornell University | |
PyRTL | Python | Based on Python, from University of California, Santa Barbara | |
ROCCC (Riverside Optimizing Compiler for Configurable Computing) | Free and open-source C to HDL tool | ||
RHDL | Ruby | Based on the Ruby programming language | |
ROHD (Rapid Open Hardware Development framework)[24] | Dart | A framework for hardware design and verification, written in Dart | |
Ruby (hardware description language) | |||
SystemC | Standardized class of C++ libraries for high-level behavioral and transaction modeling of digital hardware at a high level of abstraction, i.e. system-level
| ||
SystemVerilog | Superset of Verilog, with enhancements to address system-level design and verification | ||
SpinalHDL | Scala | Based on Scala (embedded DSL) | |
SystemTCL | SDL based on Tcl. | ||
THDL++ (Templated HDL inspired by C++) | Extension of VHDL with inheritance, advanced templates and policy classes | ||
Verik | Kotlin reinterpreted with the semantics of an HDL. It is transpiled to SystemVerilog. | ||
TL-Verilog (Transaction-Level Verilog) | Extension of Verilog/SystemVerilog with constructs for pipelines and transactions. | ||
Verilog | One of the most widely used and well-supported HDLs | ||
VHSIC HDL)
|
One of the most widely used and well-supported HDLs | ||
No longer in common use | Advanced Boolean Expression Language (ABEL) | Obsolete HDL made by Data I/O Corporation in 1983
| |
Confluence | A functional HDL, Has been discontinued | ||
CoWareC | C-based HDL by CoWare . Now discontinued in favor of SystemC
| ||
ELLA | No longer in common use | ||
ISPS | Original HDL from CMU. No longer in common use. | ||
KARL (KAiserslautern Register Language)[9] | A pascalish hardware descriptive language. No longer in common use. |
HDLs for printed circuit board design
Several projects exist for defining printed circuit board connectivity using language based, textual-entry methods.
Name | Description |
---|---|
PHDL (PCB HDL) | A free and open source HDL for defining printed circuit board connectivity |
EDAsolver | An HDL for solving schematic designs based on constraints |
SKiDL | Open source python module to design electronic circuits |
See also
References
- ISBN 9780136019282.
- ^ Barbacci, M. "A comparison of register transfer languages for describing computers and digital systems," Carnegie-Mellon Univ., Dept. of Computer Science, March 1973
- ISBN 0-07-004357-4.
- ISBN 1-57356-521-0.
- OCLC 440245727.
- )
- )
- University of Kaiserslautern.
- ^ ISBN 9789401119146
- )
- ^ "VHDL-Based FPGA Programming Application Software Tool". Annapolis Micro Systems, Inc. Retrieved 2018-12-01.
- ^ "VHDL code - HDL Coder - MATLAB & Simulink". Mathworks.com. 2011-04-30. Retrieved 2012-08-11.
- ^ "Digital Signal Processing (DSP) Builder - Intel® FPGAs". Intel. Retrieved 2021-09-20.
- ^ "System Generator for DSP". Xilinx.com. Archived from the original on 2012-07-12. Retrieved 2012-08-11.
- ^ A History of Haskell: being lazy with class §12.4.2
- ^ "Chisel/FIRRTL Hardware Compiler Framework".
- ^ "Higher-level language COLAMO | НИЦ супер-ЭВМ и нейрокомпьютеров".
- S2CID 381119.
- S2CID 14198160.
- ^ Chalmers Lava
- ^ Xilinx Lava
- ^ Kansas Lava
- ^ York Lava
- ^ "Rapid Open Hardware Development (ROHD) Framework". GitHub. 17 November 2021.
External links
- HCT - The HDL Complexity tool, used to determine design complexity.