Depletion-load NMOS logic
In
Depletion-mode n-type MOSFETs as load transistors allow single voltage operation and achieve greater speed than possible with pure enhancement-load devices. This is partly because the depletion-mode MOSFETs can be a better current source approximation than the simpler enhancement-mode transistor can, especially when no extra voltage is available (one of the reasons early PMOS and NMOS chips demanded several voltages).
The inclusion of depletion-mode NMOS transistors in the manufacturing process demanded additional manufacturing steps compared to the simpler enhancement-load circuits; this is because depletion-load devices are formed by increasing the amount of dopant in the load transistors channel region, in order to adjust their threshold voltage. This is normally performed using ion implantation.
Although the CMOS process replaced most NMOS designs during the 1980s, some depletion-load NMOS designs are still produced, typically in parallel with newer CMOS counterparts. One example of this is the Z84015[1] and Z84C15.[2]
History and background
Following the invention of the
In 1965,
Silicon gate
In the late 1960s,
NMOS and back-gate bias
There are a couple of drawbacks associated with PMOS: The
Early work on NMOS integrated circuit (IC) technology was presented in a brief
The production-ready NMOS process enabled HP to develop the industry’s first 4-kbit IC
Depletion-mode transistors
Early MOS logic had one transistor type, which is
The first depletion-load NMOS circuits were pioneered and made by the DRAM manufacturer Mostek, which made depletion-mode transistors available for the design of the original Zilog Z80 in 1975–76.[10] Mostek had the ion implantation equipment needed to create a doping profile more precise than possible with diffusion methods, so that the threshold voltage of the load transistors could be adjusted reliably. At Intel, depletion load was introduced in 1974 by Federico Faggin, an ex-Fairchild engineer and later the founder of Zilog. Depletion-load was first employed for a redesign of one of Intel's most important products at the time, a +5V-only 1Kbit NMOS SRAM called the 2102 (using more than 6000 transistors[11]). The result of this redesign was the significantly faster 2102A, where the highest performing versions of the chip had access times of less than 100ns, taking MOS memories close to the speed of bipolar RAMs for the first time.[12]
Depletion-load NMOS processes were also used by several other manufacturers to produce many incarnations of popular 8-bit, 16-bit, and 32-bit CPUs. Similarly to early PMOS and NMOS CPU designs using
A large number of support and peripheral ICs were also implemented using (often static) depletion-load based circuitry. However, there were never any standardized
Intel HMOS
Intel's own depletion-load NMOS process was known as HMOS, for High density, short channel MOS. The first version was introduced in late 1976 and first used for their
HMOS continued to be improved and went through four distinct generations. According to Intel, HMOS II (1979) provided twice the density and four times the speed/power product over other typical contemporary depletion-load NMOS processes.
The original HMOS process, later referred to as HMOS I, had a channel length of 3 microns, which was reduced to 2 for the HMOS II, and 1.5 for HMOS III. By the time HMOS III was introduced in 1982, Intel had begun a switch to their CHMOS process, a CMOS process using design elements of the HMOS lines. One final version of the system was released, HMOS-IV. A significant advantage to the HMOS line was that each generation was deliberately designed to allow existing layouts to die-shrink with no major changes. Various techniques were introduced to ensure the systems worked as the layout changed.[16][17]
HMOS, HMOS II, HMOS III, and HMOS IV were together used for many different kinds of processors; the
Further development
In the mid-1980s, faster CMOS variants, using similar HMOS process technology, such as Intel's CHMOS I, II, III, IV, etc. started to supplant n-channel HMOS for applications such as the
Compared to CMOS
Compared to static CMOS, all variants of NMOS (and PMOS) are relatively power hungry in steady state. This is because they rely on load transistors working as
Evolution from preceding NMOS types
Depletion-load processes differ from their predecessors in the way the Vdd voltage source, representing 1, connects to each gate. In both technologies, each gate contains one NMOS transistor which is permanently turned on and connected to Vdd. When the transistors connecting to 0 turn off, this pull-up transistor determines the output to be 1 by default. In standard NMOS, the pull-up is the same kind of transistor as is used for logic switches. As the output voltage approaches a value less than Vdd, it gradually switches itself off. This slows the 0 to 1 transition, resulting in a slower circuit. Depletion-load processes replace this transistor with a depletion-mode NMOS at a constant gate bias, with the gate tied directly to the source. This alternative type of transistor acts as a current source until the output approaches 1, then acts as a resistor. The result is a faster 0 to 1 transition.
Static power consumption
Depletion-load circuits consume less power than enhancement-load circuits at the same speed. In both cases the connection to 1 is always active, even when the connection to 0 is also active. This results in high static power consumption. The amount of waste depends on the strength, or physical size, of the pull-up. Both (enhancement-mode) saturated-load and depletion-mode pull-up transistors use greatest power when the output is stable at 0, so this loss is considerable. Because the strength of a depletion-mode transistor falls off less on the approach to 1, they may reach 1 faster despite starting slower, i.e. conducting less current at the beginning of the transition and at steady state.
Notes and references
- ^ See http://www.zilog.com/index.php?option=com_product&Itemid=26&mode=showProductDetails&familyId=20&productId=Z84015.
- ^ See http://www.zilog.com/index.php?option=com_product&Itemid=26&mode=showProductDetails&familyId=20&productId=Z84C15.
- ^ "1960 - Metal Oxide Semiconductor (MOS) Transistor Demonstrated". The Silicon Engine. Computer History Museum.
- ISBN 9783540342588.
- .
- .
- Apple II and the IBM PCby many years.
- ^ Shown by its mere mention in a large roundup article written by GE engineer Herman Schmid that appeared in the December, 1972 issue of IEEE Transactions on Manufacturing Technology. Although it cites Maitland’s 1970 article in Electronics, Schmid’s article does not discuss NMOS fabrication in detail but it does cover PMOS and even CMOS fabrication extensively.
- ^ "Prologues". Hp9825.com. Retrieved 2022-03-15.
- ^ Zilog relied on Mostek and Synertek to produce the Z80 and other chips before their own production facilities were ready.
- ^ Each bit demands six transistors in a typical static RAM.
- ^ See for instance: http://www.intel4004.com/sgate.htm or http://archive.computerhistory.org/resources/text/Oral_History/Faggin_Federico/Faggin_Federico_1_2_3.oral_history.2004.102658025.pdf Archived 2017-01-10 at the Wayback Machine
- ^ "Motorola Redesigns 6800" (PDF). Microcomputer Digest. 3 (2). Santa Clara, CA: Microcomputer Associates: 4. August 1976. "Motorola is redesigning the M6800 microprocessor family by adding depletion loads to increase speed and reduce the 6800 CPU size to 160 mils."
- ^ Volk, A.M.; Stoll, P.A.; Metrovich, P. (2001). "Recollections of Early Chip Development at Intel" (PDF). Intel Technology Journal. 5 (Q1).
- OCLC 7802969.
- ^ HMOS III Technology. ISSCC 82. 1982.
- S2CID 1215664.
- ^ Pseudo nMOS means that an enhancement-mode p-channel transistor with grounded gate is used in place of the depletion-mode n-channel transistor. See http://eia.udg.es/~forest/VLSI/lect.10.pdf