Itanium: Difference between revisions
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In Dec 2012, IDC released a research report stating that Itanium server shipments would remain flat through 2016, with annually shipment of 26,000 systems (a decline of over 50% compare to shipments in 2008).<ref>[http://www.pcworld.com/article/2028587/intel-shifts-gears-on-itanium-raising-questions-about-the-server-chips-future.html Intel shifts gears on Itanium, raising questions about the server chip's future]</ref> |
In Dec 2012, IDC released a research report stating that Itanium server shipments would remain flat through 2016, with annually shipment of 26,000 systems (a decline of over 50% compare to shipments in 2008).<ref>[http://www.pcworld.com/article/2028587/intel-shifts-gears-on-itanium-raising-questions-about-the-server-chips-future.html Intel shifts gears on Itanium, raising questions about the server chip's future]</ref> |
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== Architecture == |
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{{Redirect|IA-64|AMD64 and Intel64 architecture|x86-64}} |
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{{Infobox CPU architecture |
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| name=Intel Itanium Architecture |
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| designer=[[Hewlett-Packard|HP]] and [[Intel Corporation|Intel]] |
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| bits=64 |
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| introduced=2001 |
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| version= |
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| design=[[Explicitly parallel instruction computing|EPIC]] |
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| type=Register-Register |
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| encoding= |
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| branching= |
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| endianness=Selectable |
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| extensions= |
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| open= |
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| registers= |
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* 128 64-bit general purpose registers |
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* 128 82-bit floating-point registers |
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* 64 1-bit predicate registers |
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}} |
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[[Image:Itanium arch.png|thumb|The Intel Itanium architecture]] |
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Intel has extensively documented the Itanium [[instruction set]] and [[microarchitecture]],<ref>{{cite web |
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| url=http://developer.intel.com/design/itanium/manuals.htm |
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| title=Intel Itanium Processor Manuals |
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| accessdate=2007-05-16 |
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| work=[[Intel]] web site |
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}}</ref> |
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and the technical press has provided overviews.<ref name="anand"/><ref name="geek1"/> The architecture has been renamed several times during its history. HP originally called it ''PA-WideWord''. Intel later called it ''IA-64'', then ''Itanium Processor Architecture'' (IPA),<ref>{{cite web |
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| url=http://www.hpworks.org.uk/newsletter/ping-year-ago.rtf |
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| title=HPWorks Newsletter |
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| accessdate=2008-01-24 |
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| month=September |
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| year=2001 |
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}}</ref> |
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before settling on ''Intel Itanium Architecture'', but it is still widely referred to as ''IA-64''. |
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It is a 64-bit register-rich explicitly parallel architecture. The base data word is 64 bits, byte-addressable. The [[logical address]] space is 2<sup>64</sup> bytes. The architecture implements [[branch predication|predication]], [[speculative execution|speculation]], and [[branch prediction]]. It uses a hardware [[register renaming]] mechanism rather than simple register windowing for parameter passing. The same mechanism is also used to permit parallel execution of loops. Speculation, prediction, predication, and renaming are under control of the compiler: each instruction word includes extra bits for this. This approach is the distinguishing characteristic of the architecture. |
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The architecture implements 128 integer [[processor register|registers]], 128 [[floating point]] registers, 64 one-bit predicates, and eight branch registers. The floating point registers are 82 bits long to preserve precision for intermediate results. |
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=== Instruction execution === |
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Each 128-bit instruction word contains three [[instruction (computer science)|instructions]], and the fetch mechanism can read up to two instruction words per clock from the L1 [[CPU cache|cache]] into the pipeline. When the compiler can take maximum advantage of this, the processor can execute six instructions per clock cycle. The processor has thirty functional execution units in eleven groups. Each unit can execute a particular subset of the [[instruction set]], and each unit executes at a rate of one instruction per cycle unless execution stalls waiting for data. While not all units in a group execute identical subsets of the instruction set, common instructions can be executed in multiple units. |
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The execution unit groups include: |
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* Six general-purpose ALUs, two integer units, one shift unit |
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* Four data cache units |
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* Six multimedia units, two parallel shift units, one parallel multiply, one [[Hamming weight|population count]] |
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* Two 82-bit floating-point [[multiply–accumulate]] units, two [[SIMD]] floating-point multiply–accumulate units (two 32-bit operations each)<ref>Sharangpani, Harsh; Arora, Ken (2000). "Itanium Processor Microarchitecture". ''[[IEEE Micro]]''. pp. 38–39.</ref> |
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* Three branch units |
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The compiler can often group instructions into sets of six that can execute at the same time. Since the floating-point units implement a multiply–accumulate operation, a single floating point instruction can perform the work of two instructions when the application requires a multiply followed by an add: this is very common in scientific processing. When it occurs, the processor can execute four [[FLOP]]s per cycle. For example, the 800 MHz Itanium had a theoretical rating of 3.2 G[[FLOPS]] and the fastest Itanium 2, at 1.67 GHz, was rated at 6.67 GFLOPS. |
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=== Memory architecture === |
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From 2002 to 2006, Itanium 2 processors shared a common cache hierarchy. They had 16 KB of Level 1 instruction cache and 16 KB of Level 1 data cache. The L2 cache was unified (both instruction and data) and is 256 KB. The Level 3 cache was also unified and varied in size from 1.5 MB to 24 MB. The 256 KB L2 cache contains sufficient logic to handle [[semaphore (programming)|semaphore]] operations without disturbing the main [[arithmetic logic unit]] (ALU). |
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Main memory is accessed through a [[computer bus|bus]] to an off-chip [[chipset]]. The Itanium 2 bus was initially called the McKinley bus, but is now usually referred to as the Itanium bus. The speed of the bus has increased steadily with new processor releases. The bus transfers 2×128 bits per clock cycle, so the 200 MHz McKinley bus transferred 6.4 GB/s, and the 533 MHz Montecito bus transfers 17.056 GB/[[Second#International second|s]]<ref>{{cite web |
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| last=Cataldo |
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| first=Anthony |
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| title=Intel outfits Itanium processor for faster runs |
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| work=[[Electronic Engineering Times|EE Times]] |
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| date= 2001-08-30 |
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| url=http://www.eetimes.com/conf/idf/showArticle.jhtml?articleID=18306162&kc=3172 |
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| accessdate=2007-12-06 |
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}}</ref> |
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=== Architectural changes === |
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{{Redirect-distinguish|Intel VT-i|Intel VT-x}} |
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Itanium processors released prior to 2006 had hardware support for the [[IA-32]] architecture to permit support for legacy server applications, but performance for IA-32 code was much worse than for native code and also worse than the performance of contemporaneous x86 processors. In 2005, Intel developed the [[IA-32 Execution Layer]] (IA-32 EL), a software emulator that provides better performance. With Montecito, Intel therefore eliminated hardware support for IA-32 code. |
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In 2006, with the release of [[Montecito (processor)|Montecito]], Intel made a number of enhancements to the basic processor architecture including:<ref>{{cite web |
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| url=http://www.intel.com/products/processor/itanium/index.htm |
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| title=Intel product announcement |
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| accessdate=2007-05-16 |
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| work=[[Intel]] web site |
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}}{{dead link|date=November 2011}}</ref> |
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* Hardware multithreading: Each processor core maintains context for two threads of execution. When one thread stalls during memory access, the other thread can execute. Intel calls this "coarse multithreading" to distinguish it from the "[[hyper-threading]] technology" Intel integrated into some [[x86]] and [[x86-64]] microprocessors. |
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* Hardware support for [[Hardware-assisted virtualization|virtualization]]: Intel added Intel Virtualization Technology (Intel VT-i), which provides hardware assists for core virtualization functions. Virtualization allows a software "[[hypervisor]]" to run multiple operating system instances on the processor concurrently. |
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*Cache enhancements: Montecito added a split L2 cache, which included a dedicated 1 MB L2 cache for instructions. The original 256 KB L2 cache was converted to a dedicated data cache. Montecito also included up to 12 MB of on-die L3 cache. |
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== Hardware support == |
== Hardware support == |
Revision as of 17:21, 11 November 2013
General information | |
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Launched | mid-2001 |
Discontinued | present |
Common manufacturer(s) |
|
Performance | |
Max. CPU clock rate | 733 MHz to 2.53 GHz |
FSB speeds | 300 MHz to 667 MHz |
Architecture and classification | |
Instruction set | Itanium |
Physical specifications | |
Cores |
|
Itanium (
The Itanium architecture is based on explicit
Itanium-based systems have been produced by HP (the
The most recent processor, Poulson was released on November 8, 2012.Market reception
High-end server market
When first released in 2001, Itanium's performance, compared to better-established
Both Red Hat and Microsoft announced plans to drop Itanium support in their operating systems due to lack of market interest;[8][9] however, other Linux distributions such as Debian remain available for Itanium. On March 22, 2011, Oracle announced discontinuation of development on Itanium, although its technical support for its existing products would continue.[10] On October, 20 2013, Oracle has officially written about its commitment to release Oracle Database 12.1.0.1.0 on HP-UX Itanium 11.31 by early 2014.[11]
A former Intel official reported that the Itanium business had become profitable for Intel in late 2009.[12] By 2009, the chip was almost entirely deployed on servers made by HP, which had over 95% of the Itanium server market share,[6] making the main operating system for Itanium HP-UX. On March 22, 2011 Intel reaffirmed its commitment to Itanium with multiple generations of chips in development and on schedule.[13]
Other markets
Although Itanium did attain limited success in the niche market of high-end computing, Intel had originally hoped it would find broader acceptance as a replacement for the original x86 architecture.[14]
AMD chose a different direction, designing the less radical x86-64, a 64-bit extension to the existing x86 architecture, which Microsoft then supported, forcing Intel to introduce the same extensions in its own x86-based processors.[15] These designs can run existing 32-bit applications at native hardware speed, while offering support for 64-bit memory addressing and other enhancements to new applications.[6] This architecture has now become the predominant 64-bit architecture in the desktop and portable market. Although some Itanium-based workstations were initially introduced by companies such as SGI, they are no longer available.
History
Development: 1989–2000
In 1989, HP determined that
HP believed that it was no longer cost-effective for individual enterprise systems companies such as itself to develop proprietary microprocessors, so it partnered with Intel in 1994 to develop the IA-64 architecture, derived from EPIC. Intel was willing to undertake a very large development effort on IA-64 in the expectation that the resulting microprocessor would be used by the majority of enterprise systems manufacturers. HP and Intel initiated a large joint development effort with a goal of delivering the first product, Merced, in 1998.[18]
During development, Intel, HP, and industry analysts predicted that IA-64 would dominate in servers, workstations, and high-end desktops, and eventually supplant RISC and
Compaq and Silicon Graphics decided to abandon further development of the Alpha and MIPS architectures respectively in favor of migrating to IA-64.[19]Several groups developed operating systems for the architecture, including
Tru64 UNIX,[19] and Monterey/64[23] (the last three were canceled before reaching the market). By 1997, it was apparent that the IA-64 architecture and the compiler were much more difficult to implement than originally thought, and the delivery of Merced began slipping.[24] Technical difficulties included the very high transistor counts needed to support the wide instruction words and the large caches.[citation needed] There were also structural problems within the project, as the two parts of the joint team used different methodologies and had slightly different priorities.[citation needed] Since Merced was the first EPIC processor, the development effort encountered more unanticipated problems than the team was accustomed to. In addition, the EPIC concept depends on compiler capabilities that had never been implemented before, so more research was needed.[citation needed]Intel announced the official name of the processor, Itanium, on October 4, 1999.[25] Within hours, the name Itanic had been coined on a
Itanium (Merced): 2001
General information | |
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Launched | June 2001 |
Discontinued | June 2002 |
Common manufacturer(s) |
|
Performance | |
Max. CPU clock rate | 733 MHz to 800 MHz |
FSB speeds | 266 MT/s |
Cache | |
L2 cache | 96 KB |
L3 cache | 2 or 4 MB |
Architecture and classification | |
Instruction set | Itanium |
Physical specifications | |
Cores |
|
Socket(s) |
|
Products, models, variants | |
Core name(s) |
|
By the time Itanium was released in June 2001, its performance was not superior to competing RISC and CISC processors.[31] Itanium competed at the low-end (primarily 4-CPU and smaller systems) with servers based on
Only a few thousand systems using the original Merced Itanium processor were sold, due to relatively poor performance, high cost and limited software availability.[33] Recognizing that the lack of software could be a serious problem for the future, Intel made thousands of these early systems available to independent software vendors (ISVs) to stimulate development. HP and Intel brought the next-generation Itanium 2 processor to market a year later.
Itanium processor family | ||||
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2001 Itanium logo | 2002 Itanium 2 logo | 2006 Itanium 2 logo | 2008 Itanium logo | 2009 Itanium logo |
June 1, 2001 – 2006 | 2002-2006/Version 2 | 2006-2010/Version 2 | 2006-2010 | 2009-2011 |
Itanium 2: 2002–2010
General information | |
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Launched | 2002 |
Discontinued | 2010 |
Designed by | Intel |
Common manufacturer(s) |
|
Performance | |
Max. CPU clock rate | 900 MHz to 2.53 GHz |
Cache | |
L2 cache | 256 KB on Itanium2 256 KB (D) + 1 MB(I) or 512 KB (I) on (Itanium2 9x00 series) |
L3 cache | 1.5-32 MB |
Architecture and classification | |
Instruction set | Itanium |
Physical specifications | |
Cores |
|
Socket(s) |
|
Products, models, variants | |
Core name(s) |
|
The Itanium 2 processor was released in 2002, and was marketed for enterprise servers rather than for the whole gamut of high-end computing. The first Itanium 2, code-named McKinley, was jointly developed by HP and Intel. It relieved many of the performance problems of the original Itanium processor, which were mostly caused by an inefficient memory subsystem. McKinley contained 221 million transistors (of which 25 million were for logic), measured 19.5 mm by 21.6 mm (421 mm2) and was fabricated in a 180 nm, bulk CMOS process with six layers of aluminium metallization.[34]
In 2003,
Intel released a new Itanium 2 family member, codenamed Madison, in 2003. Madison used a 130 nm process and was the basis of all new Itanium processors until Montecito was released in June 2006.
In March 2005, Intel announced that it was working on a new Itanium processor, codenamed
In November 2005, the major Itanium server manufacturers joined with Intel and a number of software vendors to form the Itanium Solutions Alliance to promote the architecture and accelerate software porting.[37] The Alliance announced that its members would invest $10 billion in Itanium solutions by the end of the decade.[38]
In 2006, Intel delivered Montecito (marketed as the Itanium 2 9000 series), a dual-core processor that roughly doubled performance and decreased energy consumption by about 20 percent.[39]
Intel released the Itanium 2 9100 series, codenamed Montvale, in November 2007.[40] In May 2009 the schedule for Tukwila, its follow-on, was revised again, with release to OEMs planned for the first quarter of 2010.[41]
Itanium 9300 (Tukwila): 2010
The Itanium 9300 series processor, codenamed Tukwila, was released on 8 February 2010 with greater performance and memory capacity.[42]
The device uses a 65 nm process, includes two to four cores, up to 24
Itanium 9500 (Poulson): 2012
The Itanium 9500 series processor, codenamed Poulson, is the follow-on processor to Tukwila and was released on November 8, 2012.[46] According to Intel, it skips the
At ISSCC 2011, Intel presented a paper called, "A 32nm 3.1 Billion Transistor 12-Wide-Issue Itanium Processor for Mission Critical Servers."[49][52] Given Intel's history of disclosing details about Itanium microprocessors at ISSCC, this paper most likely refers to Poulson. Analyst David Kanter speculates that Poulson will use a new microarchitecture, with a more advanced form of multi-threading that uses as many as two threads, to improve performance for single threaded and multi-threaded workloads.[53] Some new information was released at
New information presents improvements in multithreading, resilency improvements (Instruction Replay RAS) and few new instructions (thread priority, integer instruction, cache prefetching, data access hints).In Intel's Product Change Notification (PCN) 111456-01, it listed 4 models of Itanium 9500 series CPU, which was later removed in a revised document.[56] The parts were later listed in Intel's Material Declaration Data Sheets (MDDS) database.[57] Intel later posted Itanium 9500 reference manual.[58]
The models are:[56]
Processor number | Frequency |
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9520 | 1.73 GHz |
9540 | 2.13 GHz |
9550 | 2.4 GHz |
9560 | 2.53 GHz |
In comparison with its Xeon family of server processors, Itanium has never been a high-volume product for Intel. Intel does not release production numbers. One industry analyst estimated that the production rate was 200,000 processors per year in 2007.[59]
According to
In Dec 2012, IDC released a research report stating that Itanium server shipments would remain flat through 2016, with annually shipment of 26,000 systems (a decline of over 50% compare to shipments in 2008).[63]
Hardware support
Systems
Company | Latest product | |||
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name | from | to | name | CPUs |
Compaq | 2001 | 2001 | ProLiant 590 | 1–4 |
IBM | 2001 | 2005 | x455 | 1–16 |
Dell | 2001 | 2005 | PowerEdge 7250 |
1–4 |
Hitachi |
2001 | 2008 | BladeSymphony 1000 |
1–8 |
Unisys | 2002 | 2009 | ES7000/one | 1–32 |
SGI | 2001 | 2011 | Altix 4000 | 1–2048 |
Fujitsu | 2005 | 2011 | PRIMEQUEST | 1–32 |
HP | 2001 | now | Integrity |
1–256 |
Bull | 2002 | now | NovaScale 9410 | 1–32 |
NEC | 2002 | now | nx7700i | 1–256 |
Inspur | 2010 | now | TS10000 | 2-1024 |
Huawei | 2012 | now | ???? | ???? |
As of 2012[update] only a few manufacturers offer Itanium systems, including
Chipsets
The Itanium bus interfaces to the rest of the system via a chipset. Enterprise server manufacturers differentiate their systems by designing and developing chipsets that interface the processor to memory, interconnections, and peripheral controllers. The chipset is the heart of the system-level architecture for each system design. Development of a chipset costs tens of millions of dollars and represents a major commitment to the use of the Itanium. IBM created a chipset in 2003, and Intel in 2002, but neither of them has developed chipsets to support newer technologies such as DDR2 or PCI Express.[66] Currently, modern chipsets for Itanium supporting such technologies are manufactured by HP, Fujitsu, SGI, NEC, and Hitachi.
The "Tukwila" Itanium processor model had been designed to share a common chipset with the Intel Xeon processor EX (Intel’s Xeon processor designed for four processor and larger servers). The goal is to streamline system development and reduce costs for server OEMs, many of whom develop both Itanium- and Xeon-based servers. However in 2013 this goal was pushed back to "evaluated for future implementation opportunities".[67]
Software support
Itanium is supported by the following operating systems:
- HP-UX 11i
- OpenVMS I64
- Intel 64(x86-64) port is being developed.
- multiple SUSE's SLE)
- FreeBSD[68]
- Bull GCOS 8
Itanium was also supported by these operating systems:
Microsoft announced that Windows Server 2008 R2 would be the last version of Windows Server to support the Itanium, and that it would also discontinue development of the Itanium versions of Visual Studio and SQL Server.[8] Likewise, Red Hat Enterprise Linux 5 (first released in March 2007) was the last Itanium edition of Red Hat Enterprise Linux[9] and
In late September 2012, NEC announced a return from IA64 to the previous NOAH line of proprietary mainframe processors, now produced in a quad-core variant on 40nm, called NOAH-6.[72]
Oracle Corporation announced in March 2011 that it would drop development of application software for Itanium platforms, with the explanation that "Intel management made it clear that their strategic focus is on their x86 microprocessor and that Itanium was nearing the end of its life."[10] However, a California state judge ruled that Oracle will have to continue supporting and releasing new versions of its software designed for Intel Itanium-based servers sold by Hewlett-Packard, after a settlement and release agreement between HP, Oracle and Mark Hurd had revealed that Oracle must continue to offer its product suite on HP's Itanium-based server platforms and does not confer on Oracle the discretion to decide whether to do so or not. Oracle's obligation to continue to offer its products on HP's Itanium-based server platforms lasts until such time as HP discontinues the sales of its Itanium-based servers. Oracle was ordered to port its products to HP's Itanium-based servers without charge to HP.[73]
HP sells a
To allow more software to run on the Itanium, Intel supported the development of compilers optimized for the platform, especially its own suite of compilers.[74][75] Starting in November 2010, with the introduction of new product suites, the Intel Itanium Compilers were no longer bundled with the Intel x86 compilers in a single product. Intel offers Itanium tools and Intel x86 tools, including compilers, independently in different product bundles. GCC,[76][77]
Emulation
Competition
Itanium is aimed at the
In 2005, Itanium systems accounted for about 14% of HPC systems revenue, but the percentage has declined as the industry shifts to x86-64 clusters for this application.[82]
An October 2008 paper by Gartner on the Tukwila processor stated that "...the future roadmap for Itanium looks as strong as that of any RISC peer like Power or SPARC."[83]
Supercomputers and high-performance computing
An Itanium-based computer first appeared on the list of the
Processors
Released processors
The Itanium processors show a progression in capability. Merced was a proof of concept. McKinley dramatically improved the memory hierarchy and allowed Itanium to become reasonably competitive. Madison, with the shift to a 130 nm process, allowed for enough cache space to overcome the major performance bottlenecks. Montecito, with a 90 nm process, allowed for a dual-core implementation and a major improvement in performance per watt. Montvale added three new features: core-level lockstep, demand-based switching and front-side bus frequency of up to 667 MHz.
Codename | process | Released | Clock | L2 Cache/ core |
L3 Cache/ processor |
Bus |
dies/ device |
cores/ die |
watts/ device |
Comments |
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Itanium | ||||||||||
Merced | 180 nm |
2001-06 | 733 MHz | 96 KB | none | 266 MHz | 1 | 1 | 116 | 2 MB off-die L3 cache |
800 MHz | 130 | 4 MB off-die L3 cache | ||||||||
Itanium 2 | ||||||||||
McKinley | 180 nm |
2002-07-08 | 900 MHz | 256 KB | 1.5 MB | 400 MHz | 1 | 1 | 130 | HW branchlong |
1 GHz | 3 MB | 130 | ||||||||
Madison | 130 nm |
2003-06-30 | 1.3 GHz | 3 MB | 130 | |||||
1.4 GHz | 4 MB | 130 | ||||||||
1.5 GHz | 6 MB | 130 | ||||||||
2003-09-08 | 1.4 GHz | 1.5 MB | 130 | |||||||
2004-04 | 1.4 GHz | 3 MB | 130 | |||||||
1.6 GHz | ||||||||||
Deerfield | 2003-09-08 | 1.0 GHz | 1.5 MB | 62 | Low voltage | |||||
Hondo[85] | 2004-Q1 | 1.1 GHz | 4 MB | 400 MHz | 2 | 1 | 260 | 32 MB L4 | ||
Fanwood | 2004-11-08 | 1.6 GHz | 3 MB | 533 MHz | 1 | 1 | 130 | |||
1.3 GHz | 400 MHz | 62? | Low voltage | |||||||
Madison | 2004-11-08 | 1.6 GHz | 9 MB | 400 MHz | 130 | |||||
2005-07-05 | 1.67 GHz | 6 MB | 667 MHz | 130 | ||||||
2005-07-18 | 1.67 GHz | 9 MB | 667 MHz | 130 | ||||||
Itanium 2 9000 series | ||||||||||
Montecito | 90 nm |
2006-07-18 | 1.4 GHz | 256 KB (D)+ 1 MB (I) |
6–24 MB | 400 MHz | 1 | 2 | 104 | Virtualization, Multithread, no HW IA-32 |
1.6 GHz | 533 MHz | |||||||||
Itanium 2 9100 series | ||||||||||
Montvale | 90 nm |
2007-10-31 | 1.42–1.66 GHz | 256 KB (D)+ 1 MB (I) |
8–24 MB | 400–667 MHz | 1 | 1–2 | 75–104 | Core-level lockstep, demand-based switching |
Itanium 9300 series | ||||||||||
Tukwila | 65 nm |
2010-02-08 | 1.33-1.73 GHz | 256 KB (D)+ 512 KB (I) |
10–24 MB | QPI with a speed of 4.8 GT /s |
1 | 2–4 | 130–185 | A new point-to-point processor interconnect, the Turbo Boost
|
Itanium 9500 series | ||||||||||
Poulson |
32 nm |
2012-11-08[86] | 1.73-2.53 GHz | 256 KB (D)+ 512 KB (I) |
20-32 MB | QPI with a speed of 6.4 GT /s |
1 | 4-8 | 130–170 | Doubled issue width (from 6 to 12 instructions per cycle), Instruction Replay technology, Dual-domain hyperthreading[87][88][89] |
Future processors
During the HP vs. Oracle support lawsuit, court documents unsealed by Santa Clara County Court judge revealed in 2008, Hewlett-Packard had paid Intel Corp. around $440 million to keep producing and updating Itanium microprocessors from 2009 to 2014. In 2010, the two companies signed another $250 million deal, which obliged Intel to continue making Itanium central processing units for HP's machines until 2017. Under the terms of the agreements, HP has to pay for chips it gets from Intel, while Intel launches Tukwila, Poulson, Kittson and Kittson+ chips in a bid to gradually boost performance of the platform.[90][91]
Kittson
Kittson will follow Poulson in 2014. Kittson, like Poulson, will be manufactured using Intel's 32 nm process. Few other details are known beyond the existence of the codename and the binary and socket compatibility with Poulson and Tukwila, though moving to a common socket with x86 Xeon "will be evaluated for future implementation opportunities" after Kittson.[43][92]
Timeline
- 1989:
- HP begins investigating EPIC.[18]
- 1994:
- June: HP and Intel announce partnership.[93]
- 1995:
- 1996:
- 1997:
- 1998:
- March: SCO admits HP/SCO Unix alliance is now dead.
- June: IDC predicts IA-64 systems sales will reach $30bn/yr by 2001.[16]
- June: Intel announces Merced will be delayed, from second half of 1999 to first half of 2000.[97]
- September: IBM announces it will build Merced-based machines.[98]
- October: UNIXfor IA-64.
- 1999:
- 2000:
- February: Project Trilliandelivers source code.
- June: IDC predicts Itanium systems sales will reach $25bn/yr by 2003.[16]
- July: Sun and Intel drop Solaris-on-Itanium plans.[99]
- August: AMD releases specification for x86-64, a set of 64-bit extensions to Intel's own x86 architecture intended to compete with IA-64. It will eventually market this under the name "AMD64".
- February:
- 2001:
- June: IDC predicts Itanium systems sales will reach $15bn/yr by 2004.[16]
- June: Project Monterey dies.
- July: Itanium is released.
- October: IDC predicts Itanium systems sales will reach $12bn/yr by the end of 2004.[16]
- November: IBM's 320-processor Titan NOW Cluster at National Center for Supercomputing Applications is listed on the TOP500 list at position #34.[32]
- November: Compaq delays Itanium Product release due to problems with processor.[100]
- December: Gelato is formed.
- 2002:
- March: IDC predicts Itanium systems sales will reach $5bn/yr by end 2004.[16]
- June: Itanium 2 is released.
- 2003:
- 2004:
- February: Intel announces it has been working on its own x86-64 implementation (which it will eventually market under the name "Intel 64").
- June: Intel releases its first processor with x86-64 extensions, a Xeon processor codenamed "Nocona".
- June: Thunder, a system at LLNL with 4096 Itanium 2 processors, is listed on the TOP500 list at position #2.[101]
- November: Columbia, an SGI Altix 3700 with 10160 Itanium 2 processors at NASA Ames Research Center, is listed on the TOP500 list at position #2.[102]
- December: Itanium system sales for 2004 reach $1.4bn.
- 2005:
- January: HP ports OpenVMS to Itanium[103]
- February: IBM server design drops Itanium support.[66][104]
- June: An Itanium 2 sets a record Computing blade.[105]
- September: Itanium Solutions Alliance is formed.[106]
- September: Dell exits the Itanium business.[107]
- October: Itanium server sales reach $619M/quarter in the third quarter.
- October: Intel announces one-year delays for Montecito, Montvale, and Tukwila.ref name="zdnet_2005_slip"/>
- 2006:
- 2007:
- 2009:
- December: Red Hat announces that it is dropping support for Itanium in the next release of its enterprise OS, Red Hat Enterprise Linux 6.[110]
- 2010:
- February: Intel announces the "Tukwila" Itanium 9300 series.[42]
- April: Microsoft announces phase-out of support for Itanium.[111]
- October: Intel announces new releases of Intel C++ Compiler and Intel Fortran Compiler for x86/x64, while Itanium support is only available in older versions.[112]
- 2011:
- March: Oracle Corporation announces that it will stop developing application software, middleware, and Oracle Linux for the Itanium.[10]
- March: Intel and HP reiterate their support of Itanium.[113][114]
- April: Huawei and Inspur announce that they will develop Itanium servers.[115]
- 2012:
- February: Court papers were released from a case between HP and Oracle Corporation that gave insight to the fact that HP was paying Intel $690 million to keep Itanium on life support.[116]
- SAP discontinues support for Business Objects on Itanium. SAPPAM.[117]
- September: In response to a court ruling, Oracle reinstitutes support for Oracle software on Itanium hardware.[118]
- 2013:
See also
- List of Intel Itanium microprocessors
References
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{{cite web}}
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{{cite web}}
: Check date values in:|date=
(help)
External links
- Intel Itanium Home Page
- HP Integrity Servers Home Page
- Intel Itanium Specifications
- Some undocumented Itanium 2 microarchitectural information
- IA-64 tutorial, including code examples
- Itanium Docs at HP