Complex instruction set computer
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A complex instruction set computer (CISC
Examples of CISC architectures include complex
Some designs have been regarded as borderline cases by some writers.[
Incitements and benefits
Before the RISC philosophy became prominent, many computer architects tried to bridge the so-called
New instructions
In the 1970s, analysis of high-level languages indicated compilers produced some complex corresponding machine language. It was determined that new instructions could improve performance. Some instructions were added that were never intended to be used in assembly language but fit well with compiled high-level languages. Compilers were updated to take advantage of these instructions. The benefits of semantically rich instructions with compact encodings can be seen in modern processors as well, particularly in the high-performance segment where caches are a central component (as opposed to most
Design issues
While many designs achieved the aim of higher throughput at lower cost and also allowed high-level language constructs to be expressed by fewer instructions, it was observed that this was not always the case. For instance, low-end versions of complex architectures (i.e. using less hardware) could lead to situations where it was possible to improve performance by not using a complex instruction (such as a procedure call or enter instruction) but instead using a sequence of simpler instructions.
One reason for this was that architects (microcode writers) sometimes "over-designed" assembly language instructions, including features that could not be implemented efficiently on the basic hardware available. There could, for instance, be "side effects" (above conventional flags), such as the setting of a register or memory location that was perhaps seldom used; if this was done via ordinary (non duplicated) internal buses, or even the external bus, it would demand extra cycles every time, and thus be quite inefficient.
Even in balanced high-performance designs, highly encoded and (relatively) high-level instructions could be complicated to decode and execute efficiently within a limited transistor budget. Such architectures therefore required a great deal of work on the part of the processor designer in cases where a simpler, but (typically) slower, solution based on decode tables and/or microcode sequencing is not appropriate. At a time when transistors and other components were a limited resource, this also left fewer components and less opportunity for other types of performance optimizations.
The RISC idea
The circuitry that performs the actions defined by the microcode in many (but not all) CISC processors is, in itself, a processor which in many ways is reminiscent in structure to very early CPU designs. In the early 1970s, this gave rise to ideas to return to simpler processor designs in order to make it more feasible to cope without (then relatively large and expensive) ROM tables and/or PLA structures for sequencing and/or decoding.
An early (retroactively) RISC-labeled processor (IBM 801 – IBM's Watson Research Center, mid-1970s) was a tightly pipelined simple machine originally intended to be used as an internal microcode kernel, or engine, in CISC designs,[citation needed] but also became the processor that introduced the RISC idea to a somewhat larger audience. Simplicity and regularity also in the visible instruction set would make it easier to implement overlapping processor stages (pipelining) at the machine code level (i.e. the level seen by compilers). However, pipelining at that level was already used in some high-performance CISC "supercomputers" in order to reduce the instruction cycle time (despite the complications of implementing within the limited component count and wiring complexity feasible at the time). Internal microcode execution in CISC processors, on the other hand, could be more or less pipelined depending on the particular design, and therefore more or less akin to the basic structure of RISC processors.
The CDC 6600 supercomputer, first delivered in 1965, has also been retroactively described as RISC.[2][3] It had a load–store architecture which allowed up to five loads and two stores to be in progress simultaneously under programmer control. It also had multiple function units which could operate at the same time.
Superscalar
In a more modern context, the complex variable-length encoding used by some of the typical CISC architectures makes it complicated, but still feasible, to build a
Transistors for logic, PLAs, and microcode are no longer scarce resources; only large high-speed cache memories are limited by the maximum number of transistors today. Although complex, the transistor count of CISC decoders do not grow exponentially like the total number of transistors per processor (the majority typically used for caches). Together with better tools and enhanced technologies, this has led to new implementations of highly encoded and variable-length designs without load–store limitations (i.e. non-RISC). This governs re-implementations of older architectures such as the ubiquitous x86 (see below) as well as new designs for
CISC and RISC terms
This article possibly contains original research. (November 2023) |
The terms CISC and RISC have become less meaningful with the continued evolution of both CISC and RISC designs and implementations. The first highly (or tightly) pipelined x86 implementations, the 486 designs from
Contrary to popular simplifications (present also in some academic texts,) not all CISCs are microcoded or have "complex" instructions.[citation needed] As CISC became a catch-all term meaning anything that's not a load–store (RISC) architecture, it's not the number of instructions, nor the complexity of the implementation or of the instructions, that define CISC, but that arithmetic instructions also perform memory accesses.[citation needed][4][failed verification] Compared to a small 8-bit CISC processor, a RISC floating-point instruction is complex. CISC does not even need to have complex addressing modes; 32- or 64-bit RISC processors may well have more complex addressing modes than small 8-bit CISC processors.
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See also
- Reduced instruction set computer
- One-instruction set computer
- Zero instruction set computer
- VLIW
- Microcode
- Comparison of instruction set architectures
References
- S2CID 12034303.
- ^ "Computer history: CDC 6000 series Hardware Architecture". Museum Waalsdorp. July 23, 2023. Retrieved January 19, 2024.
- ^ Anthony, Sebastian (April 10, 2012). "The history of supercomputers". ExtremeTech. Retrieved January 19, 2024.
- ^ Hennessy, John; Patterson, David. Computer Architecture: A Quantitative Approach (PDF). Archived (PDF) from the original on June 14, 2023. Retrieved June 13, 2023.
General references
- Tanenbaum, Andrew S. (2006) Structured Computer Organization, Fifth Edition, Pearson Education, Inc. Upper Saddle River, NJ.
Further reading
- Mano, M. Morris. Computer System Architecture (3rd ed.). ISBN 978-0131755635.