Penryn (microarchitecture)

Penryn
General information
Launched	November 2007; 16 years ago
Performance
Max. Core
Successor(s)	Nehalem
Support status
	Unsupported

In Intel's

Tick-Tock cycle, the 2007/2008 "Tick" was the shrink of the Core microarchitecture to 45 nanometers as CPUID model 23. In Core 2 processors, it is used with the code names Penryn (Socket P), Wolfdale (LGA 775) and Yorkfield (MCM, LGA 775), some of which are also sold as Celeron, Pentium and Xeon processors. In the Xeon brand, the Wolfdale-DP and Harpertown

code names are used for LGA 771 based MCMs with two or four active Wolfdale cores.

Architectural improvements over 65-nanometer Core 2 CPUs include a new divider with reduced latency, a new shuffle engine, and SSE4.1 instructions (some of which are enabled by the new single-cycle shuffle engine).[1]

Maximum L2 cache size per chip was increased from 4 to 6 MB, with L2 associativity increased from 16-way to 24-way. Cut-down versions with 3 MB L2 also exist, which are commonly called Penryn-3M and Wolfdale-3M as well as Yorkfield-6M, respectively. The single-core version of Penryn, listed as Penryn-L here, is not a separate model like Merom-L but a version of the Penryn-3M model with only one active core.

CPU List

Processor	Brand name	Model (list)	Cores	L2 Cache	Socket	TDP
Penryn-L	Core 2 Solo	SU3xxx	1	3 MB	BGA956	5.5 W
Penryn-3M	Core 2 Duo	SU7xxx	2	3 MB	BGA956	10 W
Penryn-3M		SU9xxx		3 MB		10 W
Penryn		SL9xxx		6 MB		17 W
Penryn		SP9xxx		6 MB		25/28 W
Penryn-3M		P7xxx		3 MB	Socket P FCBGA6	25 W
Penryn-3M		P8xxx		3 MB
Penryn		P9xxx		6 MB
Penryn-3M		T6xxx		2 MB		35 W
Penryn-3M		T8xxx		3 MB
Penryn		T9xxx		6 MB
Penryn		E8x35		6 MB	Socket P	35-55 W
Penryn-QC	Core 2 Quad	Q9xxx	4	2x3-2x6 MB	Socket P	45 W
Penryn XE	Core 2 Extreme	X9xxx	2	6 MB	Socket P	44 W
Penryn-QC	Core 2 Extreme	QX9xxx	4	2x6 MB	Socket P	45 W
Penryn-3M	Celeron	T3xxx	2	1 MB	Socket P	35 W
Penryn-3M		SU2xxx	2	1 MB	µFC-BGA 956	10 W
Penryn-L		9x0	1	1 MB	Socket P	35 W
Penryn-L		7x3	1	1 MB	µFC-BGA 956	10 W
Penryn-3M	Pentium	T4xxx	2	1 MB	Socket P	35 W
Penryn-3M		SU4xxx	2	2 MB	µFC-BGA 956	10 W
Penryn-L		SU2xxx	1	2 MB	µFC-BGA 956	5.5 W
Wolfdale-3M
	Celeron	E3xxx	2	1 MB	LGA 775	65 W
	Pentium	E2210		1 MB
		E5xxx		2 MB
		E6xxx		2 MB
	Core 2 Duo	E7xxx		3 MB
Wolfdale	Core 2 Duo	E8xxx		6 MB
Wolfdale	Xeon	31x0				45-65 W
Wolfdale-CL		30x4	1		LGA 771	30 W
Wolfdale-CL		31x3	2		LGA 771	65 W
Yorkfield	Xeon	X33x0	4	2×3–2×6 MB	LGA 775	65–95 W
Yorkfield-CL	Xeon	X33x3		2×3–2×6 MB	LGA 771	80 W
Yorkfield-6M	Core 2 Quad	Q8xxx		2×2 MB	LGA 775	65–95 W
Yorkfield-6M		Q9x0x		2×3 MB
Yorkfield		Q9x5x		2×6 MB
Yorkfield XE	Core 2 Extreme	QX9xxx		2×6 MB		130–136 W
Yorkfield XE	Core 2 Extreme	QX9xx5		2×6 MB	LGA 771	150 W
Wolfdale-DP	Xeon	E52xx	2	6 MB	LGA 771	65 W
		L52xx				20-55 W
		X52xx				80 W
Harpertown		E54xx	4	2×6 MB	LGA 771	80 W
		L54xx				40-50 W
		X54xx				120-150 W

Processor cores

The processors of the Core microarchitecture can be categorized by number of cores, cache size, and socket; each combination of these has a unique code name and product code that is used across a number of brands. For instance, code name "Allendale" with product code 80557 has two cores, 2 MB L2 cache and uses the desktop socket 775, but has been marketed as Celeron, Pentium, Core 2 and Xeon, each with different sets of features enabled. Most of the mobile and desktop processors come in two variants that differ in the size of the L2 cache, but the specific amount of L2 cache in a product can also be reduced by disabling parts at production time. Wolfdale-DP and all quad-core processors except Dunnington QC are multi-chip modules combining two dies. For the 65 nm processors, the same product code can be shared by processors with different dies, but the specific information about which one is used can be derived from the stepping.

	fab	cores	Mobile		Desktop, UP Server		CL Server	DP Server	MP Server
Single-Core 45 nm	45 nm	1		Penryn-L 80585				Wolfdale-CL 80588
Dual-Core 45 nm	45 nm	2	Penryn-3M 80577	Penryn 80576	Wolfdale-3M 80571	Wolfdale 80570	Wolfdale-CL 80588	Wolfdale-DP 80573
Quad-Core 45 nm	45 nm	4		Penryn-QC 80581	Yorkfield-6M 80580	Yorkfield 80569	Yorkfield-CL 80584	Harpertown 80574	Dunnington QC 80583
Six-Core 45 nm	45 nm	6							Dunnington 80582

Steppings using 45 nm process

Stepping	Released	Area	CPUID	L2 cache	Max. clock	Celeron	Pentium	Core 2	Celeron	Pentium	Core 2	Xeon	Core 2	Xeon	Xeon
						Mobile (Penryn)			Desktop (Wolfdale)				Desktop ( Yorkfield )		Server ( Dunnington )
C0	Nov 2007	107 mm²	10676	6 MB	3.00 GHz			X9000			E8000	3100	QX9000		5400
M0	Mar 2008	82 mm²	10676	3 MB	2.40 GHz	7xx		SU9000		E2000	E7000
C1	Mar 2008	107 mm²	10677	6 MB	3.20 GHz								QX9000	3300
M1	Mar 2008	82 mm²	10677	3 MB	2.50 GHz								Q9000	3300
E0	Aug 2008	107 mm²	1067A	6 MB	3.33 GHz			QX9000			E8000	3100	Q9000 Q9000S QX9000	3300	5400
R0	Aug 2008	82 mm²	1067A	3 MB	2.93 GHz	T3000	SU4000	SU9000	E3000	E6000	E7000		Q9000 Q9000S	3300
A1	Sep 2008	503 mm²	106D1	3 MB	2.67 GHz										7400

In the model 23 (cpuid 01067xh), Intel started marketing stepping with full (6 MB) and reduced (3 MB) L2 cache at the same time, and giving them identical cpuid values. All steppings have the new SSE4.1 instructions. Stepping C1/M1 was a bug fix version of C0/M0 specifically for quad core processors and only used in those. Stepping E0/R0 adds two new instructions (XSAVE/XRSTOR) and replaces all earlier steppings.

In mobile processors, stepping C0/M0 is only used in the Intel Mobile 965 Express (Santa Rosa refresh) platform, whereas stepping E0/R0 supports the later Intel Mobile 4 Express (Montevina) platform.

Model 29 stepping A1 (cpuid 106d1h) adds an L3 cache as well as six instead of the usual two cores, which leads to an unusually large die size of 503 mm².

Dunnington

).

Roadmap

References

^ "Intel Core 2 Extreme QX9650 - Penryn Ticks Ahead".
^ "ARK entry for Intel Xeon Processor X7460". Intel. Retrieved 14 July 2009.

[1] "Intel Core 2 Extreme QX9650 - Penryn Ticks Ahead".

[2] "ARK entry for Intel Xeon Processor X7460". Intel. Retrieved 14 July 2009.

CPU List

Processor cores

Steppings using 45 nm process

Roadmap

See also

References