NetBurst
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General information | |
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Launched | November 20, 2000 |
Performance | |
Max. 65 nm (B0) | |
Cores |
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Sockets | |
Products, models, variants | |
Models |
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History | |
Predecessor | P6 |
Successors | Intel Core IA-64 |
The NetBurst microarchitecture,[1][2] called P68 inside Intel, was the successor to the P6 microarchitecture in the x86 family of central processing units (CPUs) made by Intel. The first CPU to use this architecture was the Willamette-core Pentium 4, released on November 20, 2000 and the first of the Pentium 4 CPUs; all subsequent Pentium 4 and Pentium D variants have also been based on NetBurst. In mid-2001, Intel released the Foster core, which was also based on NetBurst, thus switching the Xeon CPUs to the new architecture as well. Pentium 4-based Celeron CPUs also use the NetBurst architecture.
NetBurst was replaced with the Core microarchitecture based on P6, released in July 2006.
Technology
The NetBurst microarchitecture includes features such as Hyper-threading, Hyper Pipelined Technology, Rapid Execution Engine, Execution Trace Cache, and replay system which all were introduced for the first time in this particular microarchitecture, and some never appeared again afterwards.
Hyper-threading
Hyper-threading is Intel's proprietary simultaneous multithreading (SMT) implementation used to improve parallelization of computations (doing multiple tasks at once) performed on x86 processors. Intel introduced it with NetBurst processors in 2002. Later Intel reintroduced it in the Nehalem microarchitecture after its absence in the Core 2.
Quad-Pumped Front-Side Bus
The Northwood and Willamette cores feature an external Front Side Bus (FSB) that runs at 100 MHz which transfers four bits per clock cycle, thus having an effective speed of 400 MHz. Later revisions of the Northwood core, along with the Prescott core (and derivatives) have an effective 800 MHz front-side bus (200 MHz quad pumped). [1]
Hyper-Pipelined Technology
The Wilamette and Northwood cores contain a 20-stage
Rapid Execution Engine
With this technology, the two arithmetic logic units (ALUs) in the core of the CPU are double-pumped, meaning that they actually operate at twice the core clock frequency. For example, in a 3.8 GHz processor, the ALUs will effectively be operating at 7.6 GHz. The reason behind this is to generally make up for the low IPC count; additionally this considerably enhances the integer performance of the CPU. Intel also replaced the high-speed barrel shifter with a shift/rotate execution unit that operates at the same frequency as the CPU core. The downside is that certain instructions are now much slower (relatively and absolutely) than before, making optimization for multiple target CPUs difficult. An example is shift and rotate operations, which suffer from the lack of a barrel shifter which was present on every x86 CPU beginning with the i386, including the main competitor processor, Athlon.
Execution Trace Cache
Within the L1 cache of the CPU, Intel incorporated its Execution Trace Cache. It stores decoded
Replay system
The replay system is a subsystem within the Intel Pentium 4 processor to catch operations that have been mistakenly sent for execution by the processor's scheduler. Operations caught by the replay system are then re-executed in a loop until the conditions necessary for their proper execution have been fulfilled.
Branch prediction hints
The Intel NetBurst architecture allows
Scaling-up issues
Despite these enhancements, the NetBurst architecture created obstacles for engineers trying to scale up its performance. With this microarchitecture, Intel planned to attain clock speeds of 10 GHz,
Revisions
Revision | Processor Brand(s) | Pipeline stages |
---|---|---|
Willamette (180 nm) | Celeron, Pentium 4, Xeon | 20 |
Northwood (130 nm) | Celeron, Pentium 4, Pentium 4 HT, Pentium 4 HT Extreme Edition, Xeon | 20 |
Prescott (90 nm) | Celeron D, Pentium 4, Pentium 4 HT, Pentium 4 HT Extreme Edition, Xeon |
31 |
Cedar Mill (65 nm) | Celeron D, Pentium 4 HT | 31 |
Smithfield (90 nm) | Pentium D, Xeon | 31 |
Presler (65 nm) | Pentium D, Xeon | 31 |
Intel replaced the original Willamette core with a redesigned version of the NetBurst microarchitecture called Northwood in January 2002. The Northwood design combined an increased cache size, a smaller 130 nm fabrication process, and Hyper-threading (although initially all models but the 3.06 GHz model had this feature disabled) to produce a more modern, higher-performing version of the NetBurst microarchitecture.
In February 2004, Intel introduced Prescott, a more radical revision of the microarchitecture. The Prescott core was produced on a 90 nm process, and included several major design changes, including the addition of an even larger cache (from 512 KB in the Northwood to 1 MB, and 2 MB in Prescott 2M), a much deeper
Intel also released a dual-core processor based on the NetBurst microarchitecture branded Pentium D. The first Pentium D core was codenamed Smithfield, which is actually two Prescott cores in a single die, and later Presler, which consists of two Cedar Mill cores on two separate dies (Cedar Mill being the 65 nm die-shrink of Prescott).
Roadmap
Successor
Intel had Netburst-based successors in development called
The Nehalem microarchitecture, the successor to the Core microarchitecture, was supposed to be an evolution of NetBurst according to Intel roadmaps dating back to 2000.[citation needed] Nehalem reimplements certain features of NetBurst, including the Hyper-Threading technology first introduced in the 3.06 GHz Northwood core, and L3 cache, first implemented on a consumer processor in the Gallatin core used in the Pentium 4 Extreme Edition.
NetBurst-based chips
- Celeron (NetBurst)
- Celeron D
- Pentium 4
- Pentium 4 Extreme Edition
- Pentium D
- Pentium Extreme Edition
- Xeon, from 2001 through 2006
See also
- Megahertz myth
- List of Intel CPU microarchitectures
- List of Intel Celeron processors (NetBurst-based)
- List of Intel Pentium 4 processors
- List of Intel Pentium D processors
- List of Intel Xeon processors (NetBurst-based)
- Tick–tock model
References
- ^ Carmean, Doug (Spring 2002). "The Intel Pentium 4 Processor" (PDF). Intel. Archived from the original (PDF) on April 19, 2018.
- ^ "Replay: Unknown Features of the NetBurst Core". XbitLabs. March 6, 2016. Archived from the original on March 6, 2016.
- ^ "The Trace Cache Branch Prediction Unit". Intel's New Pentium 4 Processor. Tom's Hardware. November 20, 2000. Retrieved April 30, 2021.
- ^ "Entering The Execution Pipeline - Pentium 4's Trace Cache, Continued". Intel's New Pentium 4 Processor. Tom's Hardware. November 20, 2000. Retrieved April 30, 2021.
- ^ Fog, Agner (December 1, 2016). "The microarchitecture of Intel, AMD and VIA CPUs" (PDF). p. 36. Retrieved March 22, 2017.
- ^ Milenkovic, Milena; Milenkovic, Aleksandar; Kulick, Jeffrey. "Demystifying Intel Branch Predictors" (PDF).
- ^ Shimpi, Anand Lal. "The future of Intel's manufacturing processes". Retrieved April 4, 2018.
- ^ "Intel says Adios to Tejas and Jayhawk chips". The Register.
- ^ Goodwins, Rupert. "Intel cancels Tejas and Jayhawk". ZDNet. Retrieved August 21, 2019.
- ^ Shilov, Anton (May 21, 2007). "The Era of Intel's NetBurst Micro-Architecture Comes to End". XbitLabs. Archived from the original on October 17, 2015. Retrieved November 29, 2015.