Program counter
The program counter (PC),[1] commonly called the instruction pointer (IP) in Intel x86 and Itanium microprocessors, and sometimes called the instruction address register (IAR),[2][1] the instruction counter,[3] or just part of the instruction sequencer,[4] is a processor register that indicates where a computer is in its program sequence.[nb 1]
Usually, the PC is incremented after fetching an
Processors usually fetch instructions sequentially from memory, but control transfer instructions change the sequence by placing a new value in the PC. These include
A branch provides that the next instruction is fetched from elsewhere in memory. A subroutine call not only branches but saves the preceding contents of the PC somewhere. A return retrieves the saved contents of the PC and places it back in the PC, resuming sequential execution with the instruction following the subroutine call.
Hardware implementation
In a simple
Like other processor registers, the PC may be a bank of binary latches, each one representing one bit of the value of the PC.[9] The number of bits (the width of the PC) relates to the processor architecture. For instance, a “32-bit” CPU may use 32 bits to be able to address 232 units of memory. On some processors, the width of program counter instead depends on the addressable memory; for example, some AVR microcontrollers have a PC which wraps around after 12 bits.[10]
If the PC is a binary counter, it may increment when a pulse is applied to its COUNT UP input, or the CPU may compute some other value and load it into the PC by a pulse to its LOAD input.[11]
To identify the current instruction, the PC may be combined with other registers that identify a
Consequences in machine architecture
Use of a PC that normally increments assumes that what a computer does is execute a usually linear sequence of instructions. Such a PC is central to the
This research also led to ways to making conventional, PC-based, CPUs run faster, including:
- Pipelining, in which different hardware in the CPU executes different phases of multiple instructions simultaneously.
- The very long instruction word (VLIW) architecture, where a single instruction can achieve multiple effects.
- Techniques to predict out-of-order execution and prepare subsequent instructions for execution outside the regular sequence.
Consequences in high-level programming
Modern high-level programming languages still follow the sequential-execution model and, indeed, a common way of identifying programming errors is with a “procedure execution” in which the programmer's finger identifies the point of execution as a PC would. The high-level language is essentially the machine language of a virtual machine,[13] too complex to be built as hardware but instead emulated or interpreted by software.
However, new programming models transcend sequential-execution programming:
- When writing a multi-threaded program, the programmer may write each thread as a sequence of instructions without specifying the timing of any instruction relative to instructions in other threads.
- In event-driven programming, the programmer may write sequences of instructions to respond to events without specifying an overall sequence for the program.
- In pipelinewithout specifying the timing relative to other sections.
See also
- Branch prediction
- Instruction cache
- Instruction cycle
- Instruction unit
- Instruction pipeline
- Instruction register
- Instruction scheduling
- Program status word
Notes
- ^ For modern processors, the concept of "where it is in its sequence" is too simplistic, as instruction-level parallelism and out-of-order execution may occur.
- ^ In a processor where the incrementation precedes the fetch, the PC points to the current instruction being executed. In some processors, the PC points some distance beyond the current instruction; for instance, in the ARM7, the value of PC visible to the programmer points beyond the current instruction and beyond the delay slot.[6]
References
- ^ ISBN 0-07-027363-4.
- ISBN 0-201-04358-0.
- ^ Principles of Operation, Type 701 and Associated Equipment (PDF). IBM. 1953.
- Van Nostrand Reinhold Company, New York, USA, LCCCN 72-153191
- ISBN 978-1-119-32091-3.
- ARM Limited. 2001. Retrieved 2019-10-18.
- ISBN 1-55860-069-8
- Springer-Verlag, Berlin, D
- McGraw-Hill Book Company, New York, USA
- AT90S8515, this means 12 bits, corresponding to 4 Kwords or 8 Kbytes. This assumption allows relative branches from the ROM's beginning to the end and vice versa which would result in an out-of-branch error when using strict arithmetics. Here, they work because the carry bits resulting from the target address computation are discarded. […] In case of the abovementioned AT90S8515, this option is even necessary because it is the only way to perform a direct jump through the complete address space […]
- ISBN 0-340-06831-0.
- ISBN 0-12-167350-2
- ISBN 0-14-005579-7