Comparison of instruction set architectures
An
An ISA defines everything a
Base
In the early decades of computing, there were computers that used binary, decimal[1] and even ternary.[2][3] Contemporary computers are almost exclusively binary.
Bits
Operands
The number of operands is one of the factors that may give an indication about the performance of the instruction set. A three-operand architecture (2-in, 1-out) will allow
A := B + C
to be computed in one instruction
ADD B, C, A
A two-operand architecture (1-in, 1-in-and-out) will allow
A := A + B
to be computed in one instruction
ADD B, A
but requires that
A := B + C
be done in two instructions
MOVE B, A ADD C, A
Encoding length
As can be seen in the table below some instructions sets keep to a very simple fixed encoding length, and other have variable-length. Usually it is
Endianness
An architecture may use "big" or "little" endianness, or both, or be configurable to use either. Little-endian processors order
Endianness only applies to processors that allow individual addressing of units of data (such as
Instruction sets
This section may be confusing or unclear to readers. In particular, Open and Royalty free are not defined and most entries are unsourced. (October 2021) |
The table below compares basic information about instruction set architectures.
Notes:
- Usually the number of registers is a power of two, e.g. 8, 16, 32. In some cases a hardwired-to-zero pseudo-register is included, as "part" of register files of architectures, mostly to simplify indexing modes. The column "Registers" only counts the integer "registers" usable by general instructions at any moment. Architectures always include special-purpose registers such as the program counter (PC). Those are not counted unless mentioned. Note that some architectures, such as SPARC, have register windows; for those architectures, the count indicates how many registers are available within a register window. Also, non-architected registers for register renaming are not counted.
- In the "Type" column, "Register–Register" is a synonym for a common type of architecture, "load–store", meaning that no instruction can directly access memory except some special ones, i.e. load to or store from register(s), with the possible exceptions of memory locking instructions for atomic operations.
- In the "Endianness" column, "Bi" means that the endianness is configurable.
Archi- tecture |
Bits | Version | Intro- duced |
Max # operands |
Type | Design | Registers (excluding FP/vector) |
Instruction encoding | Branch evaluation | Endian- ness |
Extensions | Open | Royalty free |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|
6502 | 8 | 1975 | 1 | Register–Memory | CISC | 3 | Variable (8- to 24-bit) | Condition register | Little | ||||
6800 | 8 | 1974 | 1 | Register–Memory | CISC | 3 | Variable (8- to 24-bit) | Condition register | Big | ||||
6809 | 8 | 1978 | 1 | Register–Memory | CISC | 5 | Variable (8- to 32-bit) | Condition register | Big | ||||
680x0 | 32 | 1979 | 2 | Register–Memory | CISC | 8 data and 8 address | Variable | Condition register | Big | ||||
8080
|
8 | 1974 | 2 | Register–Memory | CISC | 7 | Variable (8 to 24 bits) | Condition register | Little | ||||
8051
|
32 (8→32) | 1977? | 1 | Register–Register | CISC |
|
Variable (8 to 24 bits) | Compare and branch | Little | ||||
x86 | 16, 32, 64 (16→32→64) |
1978 | 2 (integer) 3 (AVX)[a] 4 (FMA4 and VPBLENDVPx )[4] |
Register–Memory | CISC |
|
Variable (8086 ~ 80386: variable between 1 and 6 bytes /w MMU + intel SDK, 80486: 2 to 5 bytes with prefix, pentium and onward: 2 to 4 bytes with prefix, x64: 4 bytes prefix, third party x86 emulation: 1 to 15 bytes w/o prefix & MMU . SSE/MMX: 4 bytes /w prefix AVX: 8 Bytes /w prefix) | Condition code | Little | No | No | ||
Alpha | 64 | 1992 | 3 | Register–Register | RISC | 32 (including "zero") | Fixed (32-bit) | Condition register | Bi | MVI, BWX, FIX, CIX | No | ||
ARC | 16/32/64 (32→64) | ARCv3[5] | 1996 | 3 | Register–Register | RISC | 16 or 32 including SP user can increase to 60 |
Variable (16- or 32-bit) | Compare and branch | Bi | APEX User-defined instructions | ||
ARM/A32
|
32 | ARMv1–v9 | 1983 | 3 | Register–Register | RISC |
|
Fixed (32-bit) | Condition code | Bi | NEON, TrustZone , LPAE
|
No | |
Thumb/T32
|
32 | ARMv4T-ARMv8 | 1994 | 3 | Register–Register | RISC |
|
Thumb: Fixed (16-bit), Thumb-2: Variable (16- or 32-bit) |
Condition code | Bi | NEON, TrustZone , LPAE
|
No | |
Arm64/A64
|
64 | ARMv8-A[6] | 2011[7] | 3 | Register–Register | RISC | 32 (including the stack pointer/"zero" register) | Fixed (32-bit), Variable (32-bit or 64-bit for FMA4 with 32-bit prefix[8]) | Condition code | Bi | SVE and SVE2 | No | |
AVR | 8 | 1997 | 2 | Register–Register | RISC | 32 16 on "reduced architecture" |
Variable (mostly 16-bit, four instructions are 32-bit) | Condition register, skip conditioned on an I/O or general purpose register bit, compare and skip |
Little | ||||
AVR32 | 32 | Rev 2 | 2006 | 2–3 | RISC | 15 | Variable[9] | Big | Java virtual machine | ||||
Blackfin | 32 | 2000 | 3[10] | Register–Register | RISC[11] | 2 accumulators
8 data registers 8 pointer registers 4 index registers 4 buffer registers |
Variable (16- or 32-bit) | Condition code | Little[12] | ||||
CDC Upper 3000 series
|
48 | 1963 | 3 | Register–Memory | CISC | 48-bit A reg., 48-bit Q reg., 6 15-bit B registers, miscellaneous | Variable (24- or 48-bit) | Multiple types of jump and skip | Big | ||||
CDC 6000 Central Processor (CP) |
60 | 1964 | 3 | Register–Register | n/a[b] | 24 (8 18-bit address reg., 8 18-bit index reg., 8 60-bit operand reg.) |
Variable (15-, 30-, or 60-bit) | Compare and branch | n/a[c] | Compare/Move Unit | No | No | |
CDC 6000 Peripheral Processor (PP) |
12 | 1964 | 1 or 2 | Register–Memory | CISC | 1 18-bit A register, locations 1–63 serve as index registers for some instructions | Variable (12- or 24-bit) | Test A register, test channel | n/a[d] | additional Peripheral Processing Units | No | No | |
Crusoe (native VLIW) |
32[13] | 2000 | 1 | Register–Register | VLIW[13][14] | Variable (64- or 128-bit in native mode, 15 bytes in x86 emulation)[14] | Condition code[13] | Little | |||||
Elbrus 2000 (native VLIW) |
64 | v6 | 2007 | 1 | Register–Register[13] | VLIW | 8–64 | 64 | Condition code | Little | Just-in-time dynamic translation: x87, IA-32, MMX, SSE, SSE2, x86-64, SSE3, AVX |
No | No |
DLX | 32 | ? | 1990 | 3 | ? | RISC | 32 | Fixed (32-bit) | ? | Big | ? | Yes | ? |
eSi-RISC | 16/32 | 2009 | 3 | Register–Register | RISC | 8–72 | Variable (16- or 32-bit) | Compare and branch and condition register |
Bi | User-defined instructions | No | No | |
iAPX 432[15] | 32 | 1981 | 3 | Stack machine | CISC | 0 | Variable (6 to 321 bits) | No | No | ||||
Itanium (IA-64) |
64 | 2001 | Register–Register | EPIC | 128 | Fixed (128-bit bundles with 5-bit template tag and 3 instructions, each 41-bit long) | Condition register | Bi (selectable) |
Intel Virtualization Technology | No | No | ||
LoongArch | 32, 64 | 2021 | 4 | Register–Register | RISC | 32 (including "zero") | Fixed (32-bit) | Little | No | No | |||
M32R | 32 | 1997 | 3 | Register–Register | RISC | 16 | Variable (16- or 32-bit) | Condition register | Bi | ||||
m88k | 32 | 1988 | 3 | Register–Register | RISC | Fixed (32-bit) | Big | ||||||
Mico32 | 32 | ? | 2006 | 3 | Register–Register | RISC | 32[16] | Fixed (32-bit) | Compare and branch | Big | User-defined instructions | Yes[17] | Yes |
MIPS | 64 (32→64) | 6[18][19] | 1981 | 1–3 | Register–Register | RISC | 4–32 (including "zero") | Fixed (32-bit) | Condition register | Bi | MDMX, MIPS-3D | No | No[20][21] |
MMIX | 64 | ? | 1999 | 3 | Register–Register | RISC | 256 | Fixed (32-bit) | Condition register | Big | ? | Yes | Yes |
Nios II | 32 | ? | 2000 | 3 | Register–Register | RISC | 32 | Fixed (32-bit) | Condition register | Little | Soft processor that can be instantiated on an Altera FPGA device | No | On Altera/Intel FPGA only |
NS320xx
|
32 | 1982 | 5 | Memory–Memory | CISC | 8 | Variable Huffman coded, up to 23 bytes long | Condition code | Little | BitBlt instructions | |||
OpenRISC | 32, 64 | 1.4[22] | 2000 | 3 | Register–Register | RISC | 16 or 32 | Fixed | Condition code | Bi | ? | Yes | Yes |
PA-RISC (HP/PA) |
64 (32→64) | 2.0 | 1986 | 3 | Register–Register | RISC | 32 | Fixed (32-bit) | Compare and branch | Big → Bi | MAX | No | |
PDP-8[23] | 12 | 1966 | Register–Memory | CISC | 1 accumulator
1 multiplier quotient register |
Fixed (12-bit) | Condition register
Test and branch |
EAE (Extended Arithmetic Element) | |||||
PDP-11 | 16 | 1970 | 2 | Memory–Memory | CISC | 8 (includes program counter and stack pointer, though any register can act as stack pointer) | Variable (16-, 32-, or 48-bit) | Condition code | Little | Extended Instruction Set, Floating Instruction Set, Floating Point Processor, Commercial Instruction Set | No | No | |
32/64 (32→64) | 3.1[24] | 1990 | 3 (mostly). FMA, LD/ST-Update | Register–Register | RISC | 32 GPR, 8 4-bit Condition Fields, Link Register, Counter Register | Fixed (32-bit), Variable (32- or 64-bit with the 32-bit prefix[24]) | Condition code, Branch-Counter auto-decrement | Bi | Cell , Floating-point, Matrix Multiply Assist
|
Yes | Yes | |
RISC-V | 32, 64, 128 | 20191213[25] | 2010 | 3 | Register–Register | RISC | 32 (including "zero") | Variable | Compare and branch | Little | ? | Yes | Yes |
RX
|
64/32/16 | 2000 | 3 | Memory–Memory | CISC | 4 integer + 4 address | Variable | Compare and branch | Little | No | |||
S+core
|
16/32 | 2005 | RISC | Little | |||||||||
SPARC | 64 (32→64) | OSA2017[26] | 1985 | 3 | Register–Register | RISC | 32 (including "zero") | Fixed (32-bit) | Condition code | Big → Bi | VIS | Yes | Yes[27] |
SuperH (SH) | 32 | ? | 1994 | 2 | Register–Register Register–Memory |
RISC | 16 | Fixed (16- or 32-bit), Variable | Condition code (single bit) |
Bi | ? | Yes | Yes |
System/370
z/Architecture |
64 (32→64) | 1964 | 2 (most) 3 (FMA, distinct operand facility) 4 (some vector inst.) |
Register–Memory Memory–Memory Register–Register |
CISC | 16 general 16 control (S/370 and later) 16 access (ESA/370 and later) |
Variable (16-, 32-, or 48-bit) | Condition code, compare and branch auto increment, Branch-Counter auto-decrement | Big | No | No | ||
TMS320 C6000 series | 32 | 1983 | 3 | Register-Register | VLIW | 32 on C67x 64 on C67x+ |
Fixed (256-bit bundles with 8 instructions, each 32-bit long) | Condition register | Bi | No | No | ||
Transputer | 32 (4→64) | 1987 | 1 | Stack machine | MISC | 3 (as stack) | Fixed (8-bit) | Compare and branch | Little | ||||
VAX | 32 | 1977 | 6 | Memory–Memory | CISC | 16 | Variable | Condition code, compare and branch | Little | No | |||
Z80
|
8 | 1976 | 2 | Register–Memory | CISC | 17 | Variable (8 to 32 bits) | Condition register | Little | ||||
Archi- tecture |
Bits | Version | Intro- duced |
Max # operands |
Type | Design | Registers (excluding FP/vector) |
Instruction encoding | Branch evaluation | Endian- ness |
Extensions | Open | Royalty free |
See also
- Central processing unit (CPU)
- Processor design
- Comparison of CPU microarchitectures
- Instruction set architecture
- Microprocessor
- Benchmark (computing)
Notes
- ^ The LEA (all processors) and IMUL-immediate (80186 & later) instructions accept three operands; most other instructions of the base integer ISA accept no more than two operands.
- ^ partly RISC: load/store architecture and simple addressing modes, partly CISC: three instruction lengths and no single instruction timing
- ^ Since memory is an array of 60-bit words with no means to access sub-units, big endian vs. little endian makes no sense. The optional CMU unit uses big-endian semantics.
- ^ Since memory is an array of 12-bit words with no means to access sub-units, big endian vs. little endian makes no sense.
References
- ^ da Cruz, Frank (October 18, 2004). "The IBM Naval Ordnance Research Calculator". Columbia University Computing History. Retrieved January 28, 2019.
- ^ "Russian Virtual Computer Museum – Hall of Fame – Nikolay Petrovich Brusentsov".
- ISBN 978-3-528-05757-2..
- ^ "AMD64 Architecture Programmer's Manual Volume 6: 128-Bit and 256-Bit XOP and FMA4 Instructions" (PDF). AMD. November 2009.
- ^ "Synopsys Introduces New 64-bit ARC Processor IP Delivering up to 3x Performance Increase for High-End Embedded Applications".
- ^ "ARMv8 Technology Preview" (PDF). Archived from the original (PDF) on 2018-06-10. Retrieved 2011-10-28.
- ^ "ARM goes 64-bit with new ARMv8 chip architecture". 27 October 2011. Retrieved 26 May 2012.
- ^ "Hot Chips 30 conference; Fujitsu briefing" (PDF). Toshio Yoshida. Archived from the original (PDF) on 2020-12-05.
- ^ "AVR32 Architecture Document" (PDF). Atmel. Retrieved 2008-06-15.
- ^ "Blackfin manual" (PDF). analog.com.
- ^ "Blackfin Processor Architecture Overview". Analog Devices. Retrieved 2009-05-10.
- ^ "Blackfin memory architecture". Analog Devices. Archived from the original on 2011-06-16. Retrieved 2009-12-18.
- ^ a b c d e "Crusoe Exposed: Transmeta TM5xxx Architecture 2". Real World Technologies.
- ^ a b c Alexander Klaiber (January 2000). "The Technology Behind Crusoe Processors" (PDF). Transmeta Corporation. Retrieved December 6, 2013.
- ^ Intel Corporation (1981). Introduction to the iAPX 432 Architecture (PDF). pp. iii.
- ^ "LatticeMico32 Architecture". Lattice Semiconductor. Archived from the original on 23 June 2010.
- ^ "LatticeMico32 Open Source Licensing". Lattice Semiconductor. Archived from the original on 20 June 2010.
- ^ MIPS64 Architecture for Programmers: Release 6
- ^ MIPS32 Architecture for Programmers: Release 6
- ^ MIPS Open
- ^ "Wave Computing Closes Its MIPS Open Initiative with Immediate Effect, Zero Warning".
- ^ OpenRISC Architecture Revisions
- ^ "PDP-8 Users Handbook" (PDF). bitsavers.org. 2019-02-16.
- ^ a b "Power ISA Version 3.1". openpowerfoundation.org. 2020-05-01. Retrieved 2021-10-20.
- ^ "RISC-V ISA Specifications". Retrieved 17 June 2019.
- ^ Oracle SPARC Processor Documentation
- ^ SPARC Architecture License